Web event: 28nm Silicon and Design Enablement – A Foundry and EDA Vendor Perspective
Date: October 13, 2010
Time:11:00 AM PDT
Duration: 1 hour
This webinar is the last in a series highlighting the 32/28nm design challenges and solutions starting in January 2010. It will be a joint webinar featuring speakers from Synopsys and GLOBALFOUNDRIES.
GLOBALFOUNDRIES will share their perspective on 28nm process technology and design enablement, focusing on their strengths in High K Metal Gate (HKMG) process technology, qualified IP availability and foundry readiness. Synopsys will provide an overview of their 32/28nm design solution and introduce two new in-design technologies benefitting designers at these advanced nodes; In-design STA – final stage leakage recovery, and in-design physical verification - automatic litho-repair using pattern matching technology.
After the featured presentations, there will be an audience Q&A session with the two speakers.
Synopsys Products Featured: IC Compiler and IC Validator
Who Should Attend: Design engineers
Product line managers
Place and Route design engineers
Physical Verification engineers
Ashwini Mulgaonkar Director of Marketing, Synopsys
JC Lin Vice President of Engineering, Synopsys
Walter Ng Vice President, IP Ecosystem at GLOBALFOUNDRIES