Apache Design Solutions Newsletter - September 2010

  Apache Spotlight

PathFinder™, the Industry’s First Full-chip ESD Physical Integrity Solution

PathFinder, the industry’s first comprehensive electro-static discharge (ESD) integrity solution addresses the increasing reliability challenges faced by nanometer designs. It is a layout based tool with full-chip capacity and SPICE-like accuracy. Based on proprietary modeling, extraction, and simulation technologies, PathFinder enables designers to perform early prototyping, circuit optimization, and full-chip signoff. It helps designers identify the most vulnerable area of the design, meet ESD guidelines, and improve product yield.

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 Technical Webinars

Join Apache's technology experts during our educational Webinar Series to learn about our Solutions for Ultra Low Power, Giga-hertz Performance and Advanced Reliability.

Reliability Analysis and Modeling for SoC and Custom Designs

EM analysis methodology of digital (SoC/ASIC) and custom/analog (IPs/macro) designs using Apache’s RedHawk and Totem platforms.

Sept. 14, 2010

Request the presentation (Registration required)


ESD Integrity and Verification using PathFinder

ESD verification methodology at the full-chip and IP levels from early stage to sign off using PathFinder.

Sep 21, 2010, 10:00AM PDT
For More Information and to Register  


IO Sub-system Timing and Jitter Analysis Considering Power and Signal Noise Impact

SSO analysis methodology for generating accurate timing and jitter numbers using Sentinel-SSO.

Oct 5, 2010 , 10:00AM PDT
For More Information and to Register


Chip Power Model: Next Generation Power Modeling Capabilities

Overview of Chip Power Model (CPM), an accurate and compact die model of the IC’s power deliver network, along with examples of its use for chip-package-system convergence.

Oct 12, 2010 , 10:00AM PDT
For More Information and to Register


A Design for Power (DFP™) Methodology: RTL Power Analysis and Reduction  

Design for Power (DFP) methodology including tradeoff analysis for micro-architectural decisions, “power debug” to isolate conditions causing excessive power consumption, application of analysis-driven power reduction techniques for RTL power refinement, and rigorous power regressions at full-chip level to ensure power efficiency of the entire design.

Nov 3, 2010 , 10:00AM PDT
For More Information and to Register


A Design for Power (DFP™) Methodology: Power Integrity Verification and Signoff for Low Power Designs

Detailed presentation of RedHawk’s capabilities for simulating static and dynamic analysis of designs with multiple voltage islands, VTH circuit styles, clock gating, and power gating, as well as low power debug capabilities of RedHawk Explorer.

Nov 10, 2010. 10:00AM PST
For More Information and to Register

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 Apache Technology Forum 2010

Power Methodology from RTL Design to Chip-Package Sign-off 


In this full-day multi-track technology seminar, Apache Design Solutions, along with industry leaders, will share proven methodologies for addressing the most critical design challenges faced by engineers today – power and noise management for electronic designs.

Presentations include technology roadmap for 28nm processes and beyond, advanced reliability solutions, and 3D-IC design impact on power, signal, and thermal integrity. In addition, in-depth technical discussions will offer two key requirements for design methodology – achieving ultra-low power design targets while maintaining design integrity, and meeting system cost and performance needs through integrated chip-package-system design flow.


Date: October 15, 2010
Venue: Ambassador Hotel
Hsinchu, Taiwan

For More Information and to Register  


Date: October 19, 2010
Venue: Shin Yokohama Prince Hotel
Yokohama, Kanagawa, Japan


Date: October 21, 2010
Venue: Grand Intercontinental Hotel
Seoul, Korea  

To Register  

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  In This Issue

  Upcoming Events

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  Recent News

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  • PathFinder™: A Dynamic and Static Analysis Solution for IP and Full-chip ESD Integrity

  • Power and Signal Line Electromigration Design and Reliability Validation Challenges

  • Power Noise Integrity for Analog/Mixed-Signal Designs

  • Power Noise Analysis for Next Generation ICs

  • Low Power Analysis

  • Power Closure Flow

  • Jitter & Critical Path Analysis

  • RTL Design for Power Methodology

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Customer Support

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