VHDL Coding Tips and Techniques
Abstract:
VHDL has added many new features since the publication of the first standard 22 years ago, but continues to benefit from the robustness and clarity of the original language definition. Based on experience gained from training many thousands of engineers, this webinar will help to reinforce your understanding of some of the key VHDL concepts that can make the difference between being a novice user and an expert. We will also focus on some common pitfalls and their solutions, thus helping you to make better, more efficient use of the language.
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Agenda:
- Introduction
- Coding for synthesis
- Understanding libraries, instantiation and configuration
- Understanding elaboration, generics, and parameterized structures
- Understanding processes, signals, and drivers
- Tips for working with integers and arrays
- Tips for structuring test benches
- Aldec VHDL Support (with VHDL 2008 update)
- Questions and Answers
Presenters:
Jerry Kaczynski - Aldec, Inc.
Jerry Kaczynski is a Research Engineer at Aldec, where he has been working for 18 years in the fields of HDL language and tool training, technical writing, application and research engineering. Jerry has participated in development of industry standards and has both working and teaching experience of PSL, VHDL, Verilog, SystemC and SystemVerilog.
John Aynsley- Doulos, Inc.
John Aynsley is a co-founder and CTO of Doulos, where he is a specialist in the fields of HDL-based design, system-level modeling and functional verification. John has been running VHDL training for Doulos since 1991. More recently he has focused on functional verification methodology using SystemVerilog, as well as serving as a co-author of the IEEE 1666 SystemC standard.
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