Designing Synthesizable Transactors and BFMs, July 27

 
Can you build a complete synthesizable PCIe BFM in only 7 calendar weeks with just 2 engineers?

We can... join us for this technical webinar, Designing Synthesizable Transactors and BFMs, and see how it’s done!

Date: Tuesday, July 27, 2010
Time: 10:00 am Pacific | 1:00 pm Eastern
REGISTER NOW

Learn about architecture and design considerations in building synthesizable transactors and bus functional models (BFMs) for connecting from transaction-level software to signal-level hardware interfaces such as buses or communication I/Os. See how cutting edge technology can help you connect software models and simulators with hardware in emulation. Then, explore architectural considerations for designing maintainable, correct, portable and re-usable transactors and BFMs.

Following the technical overview, sit back and watch a case study involving a synthesizable PCIe BFM that was designed in only 7 calendar weeks by two engineers. Focus will be given to addressing visibility and ensuring ease of debug, particularly when running transactors/BFMs in emulation.

What you will learn:

  • Industry standard technology for connecting software to emulation
  • Architectural considerations in designing transactors and BFMs
  • The details of a case study about building a synthesizable PCIe BFM in only 7 calendar weeks
Who should attend:

If you are involved in building synthesizable verification IP, especially transactors and BFMs, or you are involved in emulation or rapid prototyping, you should plan on attending this FREE webinar.

Date: Tuesday, July 27, 2010
Time: 10:00 am Pacific | 1:00 pm Eastern
REGISTER NOW

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