SpringSoft Technology Newsletter June 2010

Welcome to the SpringSoft Technology Newsletter. This is a monthly e-mail newsletter distributed to our customers, partners, and friends to provide information on our Novas Verification Enhancement and Laker Custom IC Design technologies. We hope the information in this newsletter will help you to use our products more effectively in your design and verification environments.

Please see the links at the end of this newsletter for subscription information or to provide feedback that will help us improve future editions.

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Verification Tips:

 Upgrade to the New Unified FSDB Dumper with Good Reasons  

 A new breed of FSDB dumper has been provided since Novas 2009.10. Different from previous FSDB dumpers, the new dumper is unified to support a broader range of simulators and versions. Currently, the new dumper can support Cadence IUS 6.2, Synopsys VCS 2006.06, Mentor Graphics ModelSim 6.4b and their later versions. This topic was originally introduced in the 2010.02 newsletter.   

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Report Power Impacted Signals 

The Verdi™ Automated Debug system supports the standard power formats, Common Power Format (CPF) and Unified Power Format (UPF), as well as the related power-aware debugging capability. This was initially introduced in the 2009.10 newsletter.

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Debug Unknowns with List Power Related X

The Verdi™ Automated Debug system supports the standard power formats, Common Power Format (CPF) and Unified Power Format (UPF), as well as the related power-aware debugging capability. This was initially introduced in the 2009.10 newsletter. 

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 New Certitude Detection Algorithm Prioritizes Faults for Early Identification of Big Weaknesses

The Certitude™ Functional Qualification System identifies holes and weaknesses in the verification environment that can let RTL bugs slip through the process undetected.  With the recent release of version 2010.04 in April, Certitude applies a new fault detection algorithm that prioritizes faults prior to qualification to enable early identification of big weaknesses in the verification environment and support an efficient incremental qualification methodology.

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Custom IC Design Tips:

Using the cdsLib Plugin from Cadence Design Systems for OpenAccess

In the 6.14 release of the Virtuoso® Layout and Schematic Editor from Cadence Design Systems, the library definition map file, lib.defs, has been replaced by the Cadence® native library definition map file, cds.lib; therefore, the lib.defs file is no longer valid for Cadence IC6.14 or later releases. This creates problems when a user mixes OpenAccess tools from other vendors.

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Technical Articles:

PRODUCT HOW-TO: Using standards-based tools to scale chip designs to next-gen geometries – Embedded.com

Layout for large digital IC designs is generally created using highly automated place-and-route (APR) tools. Although there are trade-offs for using APR instead of custom layout, the speed and confidence offered by APR far outweigh the compromises in area or performance for most designs.

But designs that require the utmost in performance and/or the smallest possible area are still done "by hand" using custom IC layout methodologies. In the next generation of custom chips, complicated rules, tight time-to-market schedules, and the sheer size and complexity of designs are making full-custom digital blocks increasingly difficult to implement.

<Read more>

Semiconductor Devices Call for Power-Aware Debug – Chip Design Magazine

Power-format standards like the Common Power Format (CPF) or Unified Power Format (UPF) have evolved as a means of dealing with the power concerns confronting today's sophisticated semiconductor designs in a more structured fashion. Both standards use TCL side files, which allow the engineer to describe the power "design." These formats, for example, allow users to specify power domains, isolation nodes, retention nodes, level-shifters, and other power-related rules. Power-format standards allow one power definition to be used throughout the design, verification, and implementation stages of the cycle. On the flip side, they also increase the complexity associated with debugging designs that are verified using this power intent files. Effectively addressing such complexity requires a debug platform that can expedite the comprehension and of power-related errors. But which debug platform and what capabilities should it feature?

  <Read more>

 A Silicon-proven Interoperable PDK – EDN Asia

On July 21, 2009, TSMC announced the availability of the industry's first interoperable process design kit (iPDK). The kit was fully validated on TSMC's 65 nanometer (nm) MS/RF process and all major EDA vendors announced their support, including Cadence, Ciranova, Magma, Mentor, SpringSoft, Synopsys, and others. On March 24, 2010, the Interoperable PDK Libraries (IPL) Alliance of which TSMC is a member, released the IPL 1.0 standard, and made the underlying technology for the TSMC iPDK available to the entire industry.

<Read more>

 Controllable Automation and Interoperability Standards: Scaling Custom Digital Layout for Next-Generation Chip Design – SoCentral.com

Layout for large digital IC designs is generally created using highly automated place-and-route (APR) tools. Although there are trade-offs for using APR instead of custom layout, the speed and confidence offered by APR far out weigh the compromises in area or performance for most designs. But designs that require the utmost in performance and/or the smallest possible area are still done "by hand" using custom IC layout methodologies.

<Read more>


News:

TSMC uses SpringSoft's Laker in 28nm AMS reference flow – EDA DesignLine

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) announced it has licensed the Laker custom layout automation system from SpringSoft Inc. for the company's 28-nanometer Analog and Mixed-Signal (AMS) Reference Flow 1.0.SpringSoft (Hsinchu, Taiwan) said its Laker software tool targets analog, mixed-signal, memory and custom digital IC design. It is claimed to provide an intuitive methodology and controllable automation to accelerate and improve layout results.

  <Read more>

 Verdi, Laker and Certitude Update

Graham Bell interviews SpringSoft Vice President of Marketing, Oz Levia, @ DAC.

<Trouble viewing the video, click here to watch>


SpringSoft Community News!

In the past few months we have added some new features to our website, have you seen them yet?

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