Hitachi Achieves 10,000 Times Performance Boost Using Cadence Technology to Verify Complex Design

SAN JOSE, CA -- (MARKET WIRE) -- Jul 19, 2010 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that electronics giant Hitachi, Ltd. established a complex and high-quality functional verification environment with a 10,000 times performance boost by using Cadence® high-level synthesis and functional verification technologies and methodologies. Hitachi engineers verified a complex subsystem, including a next-generation PCI express core, by deploying the Cadence C-to-Silicon Compiler to accelerate their testbench on the Palladium® III acceleration/emulation system. The Cadence technology enabled Hitachi to achieve a more exhaustive set of functional test cases.

"We had to deliver high-quality designs in a short time window and therefore urgently needed to develop a platform that performed at a minimum of 1,000 times faster to verify more complex and larger combinations of functional test cases," said Nobuo Tamba, Ph.D, general manager of the Design & Development Operation, Micro Device Division at Hitachi. "Working with Cadence to apply new technologies created a breakthrough for our methodology."

First, Hitachi engineers employed SystemC® and transaction-level modeling (TLM) to develop complex testbench functions such as auto-pattern generation and auto-response logic, and a scoreboard. Then they deployed Cadence high-level synthesis to generate the synthesizable testbench, accelerating overall verification on a Palladium III system with Cadence transaction-based acceleration. Utilizing high-level synthesis is critical to achieving more productive system realization, one of the main pillars of the EDA360 vision.

"The success of this massive verification effort is the result of having two great teams of engineers working together with our superior system-level technologies and methodologies," said Christopher Tice, corporate vice president and general manager at Cadence. "This experience is a great example of how Cadence and our customers work together to achieve efficient system realization."

C-to-Silicon Compiler is a next-generation high-level synthesis technology; it automatically generates synthesizable Verilog RTL from timed or untimed C/C++/SystemC. The Palladium series delivers high system throughput, verification automation, and advanced debug to perform plan- and metric-driven system-level hardware/software co-verification.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence, Palladium and the Cadence logo are registered trademarks of Cadence Design Systems, Inc., in the USA and other countries. All other marks and names are the property of their respective owners

Add to Digg Bookmark with Add to Newsvine

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.

Email Contact 

Review Article Be the first to review this article

Synopsys: Custom Compiler

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
FPGA Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Upcoming Events
Preparing for the Cognitive Era: Education, Occupation and You at SJSU Student Union Theater 211 South 9th Street San Jose CA - Oct 18, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
CST: Webinar series

Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise