Optimizing DDR2/DDR3 Board Designs using HyperLynx

 July 9, 2010
10:00 am - 11:30 am US/Pacific
View Details

Join EDA Direct and Mentor Graphics for this complimentary web seminar where we will discuss how HyperLynx 8.1 can be used to address board Signal Integrity issues to optimize your DDR2/DDR3 designs. Learn how advanced simulation technology, packaged within an easy-to-use environment, can dramatically improve your time-to-results, giving you more opportunity to innovate while meeting deadlines and cost goals.

You Will Learn

  • Powerful new features added to your toolbox for both Signal Integrity, EMI analysis and Power Integrity
  • Advanced techniques for solving signal integrity problems, including advanced DDR2/DDR3 architectures commonly implemented in FPGAs
  • Solutions to optimize your Power Distribution Network, including IR drop and decoupling strategies
  • Hyperlynx can be deployed in any PCB Design flow, including Cadence Allegro, Mentor PADS, Expedition or Altium

See first hand how the HyperLynx DDRx wizard can simplify your task of analyzing the complete DDRx IF to allow for the fastest possible signalings.

You really can solve very complex design problems in easy-to-use tools with powerful engines beneath the hood.


Kind regards,

Cuong Nguyen
EDA Direct

Also of Interest

  • Meeting the Challenges of DDRx Design On-Demand Web Seminar View Now
  • HyperLynx - Signal Integrity Analysis, Design & Simulation Web Seminar View Now
  • HyperLynx PI - Decoupling Analysis Demo View Now



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