Visit Library Technologies at DAC, Booth 580
We have presentations and demonstrations about our innovative design optimization solutions. Come to learn how our ChipTimer product reduced the gate count of SparcT1 processor by 10% while simultaneously almost doubling its frequency to 2.4Ghz under worst case conditions at 65nm.
ChipTimer: Design Optimization
This is a gates-to-gates design optimization tool. It works in three modes: in the first mode it re-structures the design using the existing library, producing an equivalent netlist with approximately 10-20% fewer gates and 10% faster timing if there is timing violation. In the second mode, it re-structures the design by introducing new cells on the fly to speed it up. In this mode you can expect almost 2X speed improvement. In the third mode, it performs in-place optimization to fix timing violations introduced by P&R and cross-talk by introducing new cells if needed. It is fully automated. Works with SDC, Verilog and interfaces to Synopsys tools for timing analysis and synthesis. Works with SOC designs, in three modes, block by block
SolutionWare: Characterization and Modeling Tools
One single tool handles logic cells, IO's and Memories! Integrated multi-core support for any simulator we support! We have also significantly improved our interfaces to various simulators to almost zero-foot-print level, using "server" mode! Our state of the art tools for cell characterization and modeling beat every other solution in speed, capabilities, reliability and ease of use, almost by consensus of all knowledgeable designers. Whatever you may need, CCS, ECSM, multi-voltage, IO or memory or signal integrity, CCS-Power, CCS-Noise, UPF etc., they can handle it. We have improved memory modeling by interfacing to Hsim, generating automatic stimuli, measuring all relevant timing, power and SI parameters without cut and paste. Best of all, we can check if your memory design has a functional problem, saving you embarrassing re-spins. We also generate Verilog and Liberty models. The new version sports various speed improvements and comes with capabilities to verify and correlate the accuracy of current source models like CCS and ECSM. Even more, it can check the accuracy, integrity and completeness of liberty libraries generated by other means.
YieldOpt : Electrical DFY/Yield Optimization/Process Variation Analysis
This is a new generation statistical analysis tool which eliminates the need for statistical timing analysis. It takes a smart approach to determine statistically the best and worst case process conditions for each cell, accounting for both global and random variations. Once the best/worst timing conditions are determined for each cell, normal cell characterization is performed to produce two libraries for traditional timing analysis. It improves timing by avoiding over-pessimism and using true worst/best conditions for each cell. It is equivalent to exhaustive Monte-Carlo. We have been able to handle as many as 800 random variables in a single run. Its run time is comparable to single corner characterization.
CellOpt: Circuit Optimizer
Put your circuit design process on auto-pilot! Our dynamic transistor level circuit optimizer CellOpt reduces power dissipation while meeting the timing requirements. From simple combinational cells to complex flops, it can generate the optimal circuit which is faster, smaller and uses less power. It can handle different logic families in addition to standard CMOS like dynamic logic and even in CML. It automatically reduces/eliminates internal glitches. Internal power dissipation is reduced by 15-50% while speeding up the circuit by 0-50%.
We also have solutions for custom block modeling and power simulation.
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