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Agenda
9:00-9:40 Introduction and Verification Challenges: Industry Keynote
Brian Bailey, BB Consulting
9:40-10:25 Customer Panel: What technologies / solutions are yielding the highest ROI?
- Laurent Arditi, ARM
- Jai Kumar, Intel
- Ali Habibi, nVidia
- Other invited: Sony, ST, Qualcomm, Broadcom, HP
10:25-10:40 Break
9:40-10:25 Customer Panel: What technologies / solutions are yielding the highest ROI?
- Laurent Arditi, ARM
- Jai Kumar, Intel
- Ali Habibi, nVidia
- Other invited: Sony, ST, Qualcomm, Broadcom, HP, &
10:25-10:40 Break
10:40-11:30 Formal Verification:
Technology Provider Presentation
Title : Advances in Formal Verification and its Widespread Adoption as a Sign-off Tool
Presenter: Rajeev Ranjan, CTO - Jasper Design Automation
Abstract : Technological advances in formal verification have led to increased controllability and observability in the design and verification process. Jasper formal verification pushes the envelope on performance and capacity with new engines, algorithms, and distributed runs across multi-threaded machines and farms. Its application is not restricted to, and has gone above and beyond the typical verification use. Formal can now be used early in the design cycle by RTL designers to gain confidence and prove the functional correctness. The advanced technologies which enable early formal use for RTL developers are behavior indexing and a persistent database, to name a few.
Customer Testimonial
Title: Formal Verification: So Many Applications
Presenter: Laurent Arditi, ARM France
Abstract: Thanks to recent improvements in the formal verification (FV) tools, this approach can now be recognized as a valuable complement to simulation-based validation. Traditional applications of FV are proofs of embedded or architectural properties. We will show how we have applied FV on the ARM CortexA9 processor in these areas, providing a fully automatic flow to maximize the number of exhaustive proofs as well as counter-examples, if any. But FV has many other applications. We will detail how it was a key methodology to answer other problems, mainly related to customer support requests.
11:30-12:20 Simulation / Testbench
Technology Provider Presentation
Title: Advanced innovations in testbench technology
Presenter: Badri Gopalan, Principal Engineer, Synopsys
Abstract: As verification complexity increases, the need for modern verification technology such as constrained random testbench, coverage, and assertions has become imminent. Synopsys has historically pioneered these technologies which have enabled users experience consistently faster and more effective verification. Now with SystemVerilog testbenches and design code exceeding 10M+ lines, Two recent innovative technologies have significantly improved functional verification: Multicore processing, in the area of verification speed; and the second, Echo Testbench Coverage Convergence, in the area of verification automation. In addition new approaches in constraint solving have significantly improved testbench runtime and capabilities. In this session, these recent technology innovations are presented and described.
Customer Testimonial
Title: VCS Echo Testbench Coverage Convergence Technology for Rapid Verification Closure
Presenter: Maruthy Vedam, Senior Staff Manager, Digital Design and Verification, Qualcomm Technologies
Abstract: Verification of todays complex digital designs forms 70% of design cycle, and as a result reducing verification time while maintaining or improving quality goals directly impacts time to market of any product. Creating coverage models, running tests and analyzing results while retaining seeds that provide good coverage are more or less manual, highly iterative, and very time consuming. VCS Echo testbench coverage convergence technology offers an automated way to address this challenge. In this presentation, the results and benefits of application of the VCS Echo technology to a recent project are shared.
12:20-13:20 Lunch
13:20-14:10 High-level Design and Verification
Technology Provider Presentation
Title: Verification from the System-Level down to Implementation
Presenter: Mark Glasser, Mentor Graphics
Customer Testimonial
Title: User Experience in High-Level Design and Verification
Presenter: Ashok Mehta, TSMC
14:10-15:00 Verification Planning
Technology Provider Presentation
Title: Verification Planning Advances Using a Metric Driven Verification Closed Loop Process
Presenter: Michael Stellfox, Distinguished Engineer, Cadence Design Systems
Abstract : The recently announced Unified Verification Methodology (UVM) provides significant benefits to the industry to increase the productivity of verification teams. One of the key system verification aspects of UVM is its ability to span transaction level (TLM) and register transfer level (RTL) abstractions. Just handling the abstractions of TLM and RTL isnt enough to provide a comprehensive verification strategy. System level verification requires the consideration of software, and hardware/software interfaces. Since the scope of the system to RTL verification problem is so broad, a systematic approach is needed for verification planning and tracking metrics that measure progress to manage successful project completion. This talk with cover the requirements and highlight solutions available today for addressing this industry challenge.
Customer Testimonial
Title: Verification Methodology and Productivity Gains using High Level Synthesis
Presenter: JC Yeh, Industrial Technology Research Institute (ITRI) and Michael Stellfox, Cadence
Abstract: High level synthesis promises productivity and IP reusability gains. An additional productivity improvement opportunity is the throughput of functional verification. This talk presents our verification methodology for design verification with high level synthesis, and experimental results when using the Cadence solution.
15:00-17:00 Coffee Break + Demonstrations + Networking
Cadence, Jasper Design Automation, Mentor Graphics, Synopsys
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