DAC Lunch-n-Learn with Mentor Silicon Test Products

Silicon  Test  and  Yield  Analysis  eNews

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Upcoming Events

Join us at DAC

Mentor at the 47th Annual Design Automation Conference (DAC)

Join us at the Design Automation Conference, in Anaheim, CA on June 14-17, 2010.
Register for User Track sessions:
  • Slash Time to Root Cause of Yield Loss with Diagnosis Driven Yield Analysis
  • A Design-centric Integrated Approach to SoC Test
Register Now

DAC Lunch-n-Learn: Memory BIST your ARM Core for Optimal Performance – Hosted by ARM and Mentor Graphics

Join us at the Design Automation Conference in Anaheim, CA on June 14-17, 2010 from 12:00pm to 1:30pm for this Lunch-n-Learn

Advanced designs today must incorporate a memory BIST and on-chip memory repair solution in order to maximize yield and minimize defects per million (DPM).

Register Now

User2User | October 6, 2010 | Austin, TX

Call for papers is now open!
User2User is a regional Mentor Graphics User Conference. This highly interactive, in-depth technical conference focuses on the needs of the entire Mentor Graphics user community. Attendees share with their colleagues their best practices, experiences, challenges, tips and tricks that they have learned about how to use our tools to design, develop and deploy high quality products.

Submitting an Abstract is Easy

Tessent YieldInsight named the EDN Innovative Product of the year 2009

In the category of design, debug, and production test, yield analysis, the finalist is the Tessent YieldInsight yield analysis tool from Mentor Graphics. The Tessent YieldInsight software product is specialized for understanding and identifying semiconductor yield loss from production scan test data.

Read more

Technical Whitepaper: Power-Aware Memory Repair

The focus technology for this month is Power Aware Memory Repair. Read more about our solution .

Did you miss the previous technology focus? How are customers using Tessent TestKompress to do low pin count test? Download now
  • Running on 3 pins – yes you can (reprinted with permission of ST Microelectronics and IEEE)
  • Combining compression with Low Pin Count Test
Multimedia Library:
Be sure to check out all the product videos on memory test online

Technical Conference Papers: View the Mentor IEEE conference papers

Read technical conference papers from Mentor Graphics recently published.

New Articles

Upcoming Training



Tessent MemoryBIST and LogicBIST Jun 9/Austin, TX
Jun 14/El Segundo, CA
Tessent Scan and ATPG Jul 13/Longmont, CO
Sep 14/Austin, TX
Tessent TestKompress and Advanced Topics Jun 8/Austin, TX
Jun 22/San Jose, CA

Customer survey – Did you take yours yet?

The Annual Customer Listening Program, provides the opportunity for customers to give feedback. If you haven’t already filled out the survey (takes 12-15 minutes to complete) please do it. In appreciation for your time, you will receive a special 50 page report prepared exclusively for Mentor Graphics by IC Insights. If you didn’t received your invitation, please Email Contact .

Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

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Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper

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