This is your opportunity to learn more about Virage Logic's powerful new solution to help increase chip bring-up efficiency. Virage Logic will showcase a live demonstration of this new option to its industry standard STARTM Memory System for post silicon bring-up and system debug.
Virage Logic Booth # 417
International Test Conference
November 1-6, 2009
Austin Convention Center
Austin, TX
Exhibit Hours
November 3rd: 10:30am - 5:30pm
November 4th: 9:30am - 5:30pm
November 5th: 9:30am - 2:00pm
Since the introduction of the STAR Memory System in 2001, Virage Logic has been providing industry leading embedded memory test, diagnosis and repair solutions that help IDMs, fabless houses and foundries accelerate their ramp to volume production. With this new option Virage Logic delivers an even more comprehensive end-to-end solution to assist our users with the entire SoC realization process from initial design planning all the way through post silicon bring up and volume manufacturing.
Hear one of the industry's foremost experts, Virage Logic's Dr. Yervant Zorian, Vice President and Chief Scientist, address these challenging issues at ITC:
Sunday, November 1st
Tutorial 4: System-in-Package Test Strategies
8:30am - 4:30pm
Tuesday, November 3rd
Panel 3: Testing of 3-D Chips: Is There Anything New Under the Sun?
4:00pm - 5:30pm
Wednesday, November 4th
Embedded Tutorial 1: Testing 3-D Chips Containing Through-Silicon Vias
8:30am - 10:00am
Session 7: Embedded Memory Test & Repair
8:30am - 10:00am
Virage Logic Exhibitor Presentation: An End-to-End Solution for Yield Optimization
10:00am - 10:30am
Management Session: Decision Making Trade-Offs and Choices for Testing Today's Most Complex Chips
4:00pm - 6:00pm
Thursday & Friday, November 5th & 6th
DRV: 2nd IEEE International Workshop on Design for Reliability and Variability
2:00pm - 9:00pm
TVHSAC: IEEE International Workshop on Test and Validation of High-Speed Analog Circuits
2:00pm - 9:00pm
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