The new technology enables package designers, package design services companies, and offshore assembly and test companies (OSAT) to participate in the multi-die SiP design chain using a co-design methodology. It enables data to be passed easily among design chain partners using Cadence co-design technology. Companies deploying version 16.3 can benefit from shorter design cycles, improved productivity and reduced costs.
"We are looking forward to adopting the 16.3 release so we can improve our productivity and provide better IC package co-design service to our customers," said CT Chiu, R&D product design manager of Advanced Semiconductor Engineering (ASE). "We anticipate the new Cadence SiP and IC packaging technology to play an important role in streamlining the semiconductor design chain."
For design miniaturization, SiP Layout XL delivers significant new capabilities to package designers. The co-design technology allows them to visualize a fully editable IC abstract including IO pad ring, bump matrix, and RDL connectivity directly from within the package environment, then propose engineering change order (ECO) edits back to the IC design team. Super-smooth routing technology helps miniaturize designs through greater route density while producing tapeout-ready routes. Assembly rule checking incorporated into the Allegro Constraint Manager helps ensure miniaturized designs can be checked against assembly rules from the common constraint environment, and SiP Layout XL includes 3D viewing and team design, and is provided equivalently to design teams working on Windows, Unix, or Linux computing platforms.
Additional highlights of the latest software release include wirebond improvements that facilitate the wirebonding of leadframe designs. Also, Allegro Package Designer now features a SiP finishing mode where an SiP design can be read, with substrate editing enabled to allow APD users to prepare a SiP design for final artwork/tapeout and design for manufacturing preparation.
"We've packed this latest release with significant new capabilities that can help package designers serve as true, value-add partners in co-design," said Keith Felton, product marketing group director at Cadence. "Deploying the latest Cadence SiP and Allegro Package Designer software helps make these engineers an important link in the semiconductor design chain."
The Allegro SiP and IC Packaging 16.3 release will be available in early December 2009.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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For more information, please contact: Dean Solov Cadence Design Systems, Inc. 408-944-7226 Email Contact