IC Package Designers Boost Productivity With New Cadence Allegro SiP and IC Packaging Software

SAN JOSE, CA -- (MARKET WIRE) -- Oct 27, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that package designers will be able to play a greater role in co-design and design chain collaboration with the latest release of its system-in-package (SiP) and IC packaging software. The Cadence® Allegro® 16.3 release features SiP Layout XL, a new product that puts co-design directly in the package design environment. The new co-design technology enables the optimization of designs between packaging and IC design teams without requiring packaging designers to learn IC design tools. Design chain collaboration is further enhanced through new SiP Finishing technology available with Allegro Package Designer (APD).

The new technology enables package designers, package design services companies, and offshore assembly and test companies (OSAT) to participate in the multi-die SiP design chain using a co-design methodology. It enables data to be passed easily among design chain partners using Cadence co-design technology. Companies deploying version 16.3 can benefit from shorter design cycles, improved productivity and reduced costs.

"We are looking forward to adopting the 16.3 release so we can improve our productivity and provide better IC package co-design service to our customers," said CT Chiu, R&D product design manager of Advanced Semiconductor Engineering (ASE). "We anticipate the new Cadence SiP and IC packaging technology to play an important role in streamlining the semiconductor design chain."

For design miniaturization, SiP Layout XL delivers significant new capabilities to package designers. The co-design technology allows them to visualize a fully editable IC abstract including IO pad ring, bump matrix, and RDL connectivity directly from within the package environment, then propose engineering change order (ECO) edits back to the IC design team. Super-smooth routing technology helps miniaturize designs through greater route density while producing tapeout-ready routes. Assembly rule checking incorporated into the Allegro Constraint Manager helps ensure miniaturized designs can be checked against assembly rules from the common constraint environment, and SiP Layout XL includes 3D viewing and team design, and is provided equivalently to design teams working on Windows, Unix, or Linux computing platforms.

Additional highlights of the latest software release include wirebond improvements that facilitate the wirebonding of leadframe designs. Also, Allegro Package Designer now features a SiP finishing mode where an SiP design can be read, with substrate editing enabled to allow APD users to prepare a SiP design for final artwork/tapeout and design for manufacturing preparation.

"We've packed this latest release with significant new capabilities that can help package designers serve as true, value-add partners in co-design," said Keith Felton, product marketing group director at Cadence. "Deploying the latest Cadence SiP and Allegro Package Designer software helps make these engineers an important link in the semiconductor design chain."

The Allegro SiP and IC Packaging 16.3 release will be available in early December 2009.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo and Allegro are registered trademarks of Cadence Design Systems, Inc., in the USA and other countries. All other marks and names are the property of their respective owners.

Image Available: http://www2.marketwire.com/mw/frame_mw?attachid=1099293

Add to Digg Bookmark with del.icio.us Add to Newsvine

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226

Email Contact





Review Article Be the first to review this article
Featured Video
Editorial
More Editorial  
Jobs
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
Verification Engineer for Ambarella at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Technical Support Engineer Germany/UK for EDA Careers at San Jose, CA
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy