Welcome to the September issue of IP Times – your source for semiconductor Intellectual Property (IP) news, trends, and developments – from the semiconductor industry’s trusted IP partner. Find out the latest news from Virage Logic!
The Sure Path to 40nm Success
Download a copy of this latest brochure from Virage Logic that features the company’s broad portfolio of 40-nanometer (nm) semiconductor IP offerings to help you address your needs at this advanced process node.
Take the Sure Path to 40nm Success NOW!
STAR™ Yield Accelerator Class – October 14, 2009
Virage Logic’s new STAR Yield Accelerator course provides training for optimal utilization of the STAR Memory System’s capabilities, based on the test and diagnostics automation tools available from Virage Logic’s STAR Yield Accelerator software package for manufacturing test. This one-day course features a combination of interactive lectures and hands-on labs.
STAR™ Memory System Class – November 10-11, 2009
Sign up today for this extensive two-day course featuring lectures, hands-on tutorials and labs that instruct you on how to integrate the STAR Memory System into your System-on-Chip (SoC) designs and accelerate your silicon success. STAR Memory System customers have improved yields by up to 250%, so don’t miss this opportunity to learn how you can effectively implement this solution to help increase yields.
SiPro™ Product Portfolio – Advanced Interface IP Solutions
Learn more about Virage Logic's SiPro product line that has been production-proven in high performance, low power and high-volume implementations at the most advanced process nodes to lower cost, improve performance and reduce power in complex SoC and ASIC designs. Offering complete solutions with Physical Layers (PHYs), controllers, I/Os, software application programming interfaces (APIs) and flexible verification options, Virage Logic's SiPro product portfolio is ideal for silicon design architects who require robust, production-proven, standards-based interface IP that minimizes area and power consumption, yet has all the necessary certification and verification tools, all available from a single supplier. Learn more, get a white paper, or watch a video!
Virage Logic Power Forward Initiative (PFI) eBook – Chapter 16
Read the new PFI eBook chapter from Virage Logic, “Minimizing Design Complexity with Power-Optimized Physical IP.” This chapter addresses the power problem and the complexity of designing with multiple power domains in SoC designs that contain memory and logic blocks, plus much more! Read more.
Virage Logic in the News
Virage Rolls New Interface IP Products – Dylan McGrath, EE Times
Virage Logic announced new interface IP products to join its SiPro product line, the group of products that have sprung from the company's January licensing agreement with Advanced Micro Devices Inc. (AMD).
Read the article.
New Business Models Emerge – Ed Sperling, Low-Power Design Community
Globalization, complexity and the rising cost of chip development are changing business models across the semiconductor design world in some expected as well as some unusual ways. On a global basis, each new process node propels a new wave of disaggregation and disruption as the costs of design continue to skyrocket. What used to be under one roof is now shared by many. This trend is hardly new. Read the article.
Power Management – Paul Buckley, DesignLine Europe, EE Times
Virage Logic and SMIC have created a radio-frequency identification (RFID) optimized version of Virage Logic's AEON Embedded Multi-Time Programmable (MTP) Non-Volatile Memory (NVM) solution. The RFID-optimized NVM solution, ideal for use in passive tags, is being developed on SMIC's 180-nanometer low leakage (LL) process, which provides enhanced RF performance. Read the article.
Virage Logic Expands SiPro™ Product Portfolio with New Production-Proven Advanced Interface IP Offerings
Virage Logic recently announced new additions to its SiPro product line of production-proven advanced interface IP. The expanded product line now includes complete standards-based solutions for PCI Express (PCIe) and Mobile Industry Processor Interface (MIPI(R)), as well as a unique multi-protocol IP solution for High-Definition Multimedia Interface (HDMI), Digital Visual Interface (DVI) and DisplayPort interfaces. Read more.
SMIC Selects Virage Logic’s AEON® Embedded Multi-Time Programmable (MTP)
Non-Volatile Memory (NVM) for RFID Applications
SMIC recently announced a radio-frequency identification (RFID) optimized version of Virage Logic's AEON MTP NVM solution. The RFID-optimized NVM solution, ideal for use in passive tags, is being developed on SMIC's 180-nanometer (nm) low leakage (LL) process, which provides enhanced RF performance. Virage Logic's AEON/MTP RFID is based on a single-poly standard logic CMOS process that eliminates costly manufacturing steps normally involved with floating-gate memory, thus reducing engineering effort and associated costs of integrating NVM into RFID designs. Read more.
Upcoming Industry Events
As the industry’s trusted semiconductor IP partner, Virage Logic participates in a variety of global industry events to help educate the SoC design community on the latest advanced IP technology. See below for a list of upcoming events where you can hear Virage Logic’s IP experts address the complex issues facing the industry today.
Global Semiconductor Alliance (GSA) Expo & Conference
October 1, 2009 – Booth #802
Santa Clara Convention Center, Santa Clara, California
The Virage Logic IP experts will be exhibiting at the GSA Expo & Conference (booth #802) to highlight the latest developments in advanced IP technology. Stop by to meet the team and hear more about our embedded SRAMs, embedded NVMs, embedded memory test and repair, logic libraries, memory development software, and advanced interface IP solutions. Don’t miss the live demo featuring Virage Logic’s latest SiPro™ interface IP! Register.
Virage Logic’s VIP Partner Program brings together technology and business alliances with our industry partners for the benefit of our mutual customers. As part of the VIP Partner Program, Virage Logic supports our partners’ global events, such as the ones listed below.
Japan Synopsys Users Group (JSNUG)
October 14, 2009 – Tokyo, Japan
Visit the Virage Logic experts at JSNUG, an open forum to exchange ideas and explore solutions that focus on real-world design challenges. Learn about Virage Logic’s advanced technology IP solutions to help you accelerate your time-to-market with production proven technology. Register.
SMIC 2009 Technology Symposiums China
October 15, 2009 – Beijing, China
October 23, 2009 – Shanghai, China
Join the Virage Logic IP experts to learn about advanced IP solutions to help you address your complex design challenges. Let us show you how we can meet your specific design needs, and don’t miss Virage Logic’s featured speaker on our Non-Volatile Memory Solutions! Register.
Power Forward Low-Power Design Summit
October 20, 2009 – Silicon Valley
Cadence Design Systems, Bldg 10 Auditorium, San Jose, California
The second annual Low-Power Design Summit will feature Power Forward Initiative (PFI) member companies who will share their low-power design expertise best practices and proven capabilities that you can adopt to design energy-efficient wireless and wired electronics. Virage Logic will have several featured speakers at this interactive event discussing critical low-power topics. Register.