EDA Industry Update JUNE 2009 -- What did the Last Quarter Bring?
by Dr. Russ Henke and Dr. Jack Horgan
In each of the 24 quarterly EDA Industry Commentaries published here since May 2003 by the authors, the then-current yearly and quarterly financial performances of a selected group of publicly traded Electronic Design Automation (EDA) companies were analyzed and compared. Expectations regarding the future financial performances of these same EDA entities were documented as well. The originally selected companies were
Altium, Ansoft, Cadence, Magma, Mentor Graphics, Nassda, Synopsys, Synplicity and
Verisity.
Note that only Qualcomm (+15%) and STMicroelectronics (+3.3%) experienced revenue growth relative to the prior year. Total 2009 revenue from all firms surveyed by iSuppli was $258 billion, a decline of 5.2% from 2007. On May 01, 2009 the Semiconductor Industry Association (SIA) reported that worldwide sales of semiconductors were $14.7 billion in March 2009, a slight gain of 3.3% from the prior month when sales were $14.2 billion. Sales for the entire first quarter of 2009 amounted to $44.0 billion, a disappointing 29.9% decline from the first quarter of 2008 when sales were $62.8 billion. Q1 2009 sales also declined by 15.7% from the fourth quarter of 2008 when sales were $52.2 billion. March sales in all geographic regions except Japan showed month-to-month gains. Sales in Japan were sharply lower, reflecting a drop in the country’s economic output. However, all geographic regions reported lower first-quarter sales compared to the same period of 2008. SIA President George Scalise said, “The modest sequential rebound in worldwide sales in March suggests that demand has stabilized somewhat, albeit at substantially lower levels than last year. While all major product sectors showed month-on-month growth, there continues to be limited visibility in end markets. There are some bright spots such as ‘smart phones’ and ‘netbook’ PCs, but there are no clear signs of early firming of demand in other major end markets such as automotive, corporate information technology, and consumer electronics. Scalise continued, “The global chip industry continues to reflect the influence of the worldwide economic slowdown. We expect economic stimulus measures in the U.S. combined with other countries will begin to impact sales as we enter 2010.” On June 01, 2009 Cadence announced that the Chinese Academy of Sciences Institute of Computing Technology (ICT) had adopted the Cadence® Incisive® Xtreme® III System for accelerating the development of RTL design with a verification flow for its next-generation 64 million-plus gates Loongson III advanced multi-core microprocessor. The deployment of the Incisive Xtreme III System for developing the ICT’s advanced 65- and 45-nanometer multi-core processor is said to have enabled ICT engineers to accelerate system-level verification while validating software operations. On May 27, 2009 Magma announced the release of Talus ® 1.1, a new RTL-to-GDSII chip implementation system that is said to deliver the fastest timing closure on the largest and most complex semiconductor designs. Talus 1.1 utilizes the new Talus ® COre ™ technology, which leverages Magma's unified data model to perform timing optimization concurrently during routing. This is said to enhance designers' ability to achieve optimal results across a wide variety of designs -- while minimizing the need for user intervention. Talus 1.1 also introduces the Talus ® Flow Manager ™ with "out-of-the-box" design flows. Included with the release are out-of-the-box reference flows for RTL-to-GDSII, multi-Vdd, low-power design and high-performance design. Talus Flow Manager also introduces a new visual analysis environment, Talus ® Visual Volcano ™, that is said to integrate and present all design and analysis data via a common display. On June 02, 2009 Synopsys announced that Semiconductor Manufacturing International Corporation (SMIC), one of the leading semiconductor foundries in the world, had adopted Synopsys' HSPICE® circuit simulator and WaveView Analyzer for design and verification of SMIC’s 65-nanometer (nm) and 45-nm IP blocks, I/O circuitry and standard cell characterization flows. Taking advantage of the features in the 2009.03 release of the Synopsys HSPICE circuit simulator, it is said that SMIC was able to cut simulation runtimes in half with improved silicon correlation over SMIC’s existing solution. How did the G5 EDA Vendors fair during the First Quarter of 2009?
Be the first to review this article
|
|||||||||
|
|||||||||
|
|||||||||