Published by Springer, a leading publisher of science, technology and medicine reference books, the book will make its debut at the DATE 2009 Conference (April 20-24, Nice, France) and can be ordered through Springer's distribution channels at: http://www.springer.com/engineering/circuits+%26+systems/book/978-0-387-93819-6.
"Timing closure is among the most pressing challenges designers face. We are proud of the work our team has done over the years in the area of timing verification, and it's been an important part of our design methodology that has enabled eSilicon to deliver working chips to so many customers on time and to budget," said Prasad Subramaniam, vice president of design technology at eSilicon. "This book reflects the expertise and experience of two of our finest engineering team members and demonstrates the quality of talent we apply to customers' projects every day."
The book provides in-depth chapters on topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. It also looks at verification of hierarchal building blocks and the full chip, including timing verification of special IO interfaces. Appendices provide complete coverage of important industry standards, such as the SDC, SDF, and SPEF formats.
"The eSilicon team has made a valuable contribution to the portfolio of books available from Springer, filling a void in quality reference material available for a specific chip design discipline. The book will be a useful tool for all levels of engineers, and provides a true hands-on guide to static timing analysis illustrated with actual design examples relevant for nanometer applications," said Alex Greene, publishing director for engineering at Springer.
The book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful.
About the authors
J. Bhasker is an expert in the area of hardware description languages and RTL synthesis. He has written a number of books on these topics. He has also been a distinguished member of the technical staff at Bell Laboratories. He has published a number of papers in journals and conferences, mostly in the area of design automation and high-level synthesis algorithms. He has been the chair of two working groups: the IEEE 1076.6 VHDL Synthesis Working Group and the IEEE 1364.1 Verilog Synthesis Working Group. He was also a major contributor to the IEEE Std 1076.3 NUMERIC packages. He was awarded the IEEE Computer Society Outstanding Contribution Award in 2005. He holds a Ph.D. degree in Computer Science from the University of Minnesota.
Rakesh Chadha has over 25 years experience in areas of timing and signal integrity at Bell Laboratories, Cadence and eSilicon. He was responsible for the timing and signal integrity for the Sematech project on Chip Parasitic Extraction and Signal Integrity Verification. Since 2000, he is Director of Design Technology at eSilicon Corporation where he has led complex ASIC projects in 90nm and 65nm process technologies. He holds a Ph.D. degree in Electrical Engineering from Indian Institute of Technology Kanpur.
eSilicon, a leading Value Chain Producer (VCP) for the semiconductor industry, provides a comprehensive suite of design, productization and manufacturing services, enabling a flexible, low-cost, lower-risk path to volume chip production. The company delivers custom chips (ASICs) to system OEMs and fabless semiconductor companies who serve a wide variety of markets including the consumer, computer, communications and industrial segments. For more information, please go to www.esilicon.com.
eSilicon is a registered trademark of eSilicon Corporation. Other trademarks are the property of their respective owners.
For more information, contact: Patrick Soheili Email Contact 408-626-4629 Mike Sottak Email Contact 408-876-4418