Real-world customer applications have seen utilization improvements of between 33 and 100 percent with the addition of MemMax Scheduler to simple memory controller systems. The new release supports data rates for DDR3-1600 Mbps and overall DRAM data transfer utilization in excess of 85 percent with heterogeneous multicore traffic.
“One of the interesting trends in the SoC market is the incorporation of ever higher numbers of CPU cores – the so-called ‘multicore’ experience, onto performance SoCs,” said Richard Wawrzyniak, senior analyst at Semico Research. “As the number of CPUs increase, this can create a troublesome bottleneck in the system architecture without a robust memory scheduler solution, such as Sonics MemMax. A robust solution in this area of SoC design can yield a significant improvement in bandwidth utilization and overall system throughput.”
The MemMax Scheduler efficiently supports a wide-range of memory traffic, including video and graphics data flows that access two-dimensional data structures. MemMax natively supports both 2D block bursts and address tiling features that improve memory access utilization by maximizing the number of page hits and hiding page miss delays. Additionally, MemMax Scheduler adds support for XOR burst sequences, which minimizes cache miss latency for DDR3 DRAMs and is configurable on a per thread basis allowing chip architects to perform delicate QoS trade-offs between memory utilization and latency minimization.
“Memory performance within the SoC is becoming the major driver of overall system performance,” said Drew Wingard, CTO at Sonics. “In high-end applications such as HDTV or set-top box SoCs, sharing scarce memory resources among the large number of cores is key to achieving that performance. Our MemMax Scheduler adds critical new capabilities to address these markets helping our customer solve a key design issue.”
MemMax Scheduler is built on the proven architecture of previous versions of MemMax and works in conjunction with Sonics’ line of on-chip communications solutions, providing customers with a complete package of tools and IP products designed to optimize the implementation of complex SoCs. Additionally, SystemC models are available for advanced architecture modeling.
As a member of the Sonics IP family, MemMax Scheduler configuration and modeling is available through the SonicsStudio™ Development Environment. SonicsStudio enables SoC developers complete data flow analysis for the memory subsystem and their entire SoC for both RTL and SystemC. With these tools and IP, Sonics’ customers can significantly reduce their project risk and overall development time.
MemMax Memory Scheduler 3.0 is available now. For more information please contact, Email Contact.
Sonics, Inc. provides SoC designers with critical semiconductor IP that is uniquely designed to optimize memory access and increase SoC performance in advanced digital consumer, wireless and mobile devices. Sonics' customers see the benefits of high design predictability and increased design efficiency. The company's broad array of on-chip connectivity solutions address the growing complexity found in consumer devices with advanced voice, data and video features. Major semiconductor and systems companies, including Broadcom, Samsung, Texas Instruments and Toshiba, leverage Sonics' technology in leading products in the wireless, digital multimedia and communications markets. For more information please visit www.sonicsinc.com.
®Sonics, Inc., the company’s logo, and SMART Interconnect are registered trademarks of Sonics, Inc. All other trademarks are the property of their respective owners.
Fast Forward Public Relations
Mary Jane Reiter, 408-725-1239