Synfora CTO to Give Tutorial on Reducing Design Time with Algorithmic Synthesis at ESC Silicon Valley

MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—March 24, 2009— At the Embedded Systems Conference (ESC) on March 31, 2009, in San Jose, California, Vinod Kathail, Chief Technology Officer at Synfora, Inc., will be giving a tutorial on algorithmic synthesis tools and methodologies that allow the design and verification of application accelerators directly from sequential C algorithms.

 

The presentation, “Algorithmic Synthesis of Application Engines from C/C++ Algorithms,” will be given at 8:00 AM as part of the “Improve Productivity at the HW/SW Interface” track. It will discuss the use of algorithmic synthesis to design complex, multi-block application accelerators and their associated bus/memory/stream interconnects from C algorithms, including the verification and system validation of the resulting RTL.

Who:

  Synfora, Inc.
     

What:

  Technical presentation on using algorithmic synthesis to reduce design and verification time of multi-block application accelerators
     

When:

  Tuesday, March 31, 2009, 8:00 AM -- 9:15 AM
     

Where:

  Embedded Systems Conference (ESC) Silicon Valley 2009
    McEnery Convention Center
    San Jose, California
    Room C3
     

The ESC Silicon Valley 2009 is being held March 30 – April 2 at the McEnery Convention Center in San Jose, California.

About Synfora, Inc.

Synfora, Inc. is the premier provider of algorithmic synthesis tools used to design complex systems-on-chips (SoCs) and FPGAs. Synfora's technology helps to reduce design costs, dramatically speed chip development, and reduce time-to-market. Synfora serves customers worldwide in the audio, video, imaging, wireless, and security segments of the integrated circuit (IC) design market. The company's investors are ATA Ventures, Foundation Capital, U.S. Venture Partners, Wafra, and Xilinx. For the latest information on Synfora, please visit http://www.synfora.com.

 



Contact:

PR for Synfora, Inc. – Cayenne Communication LLC
Michelle Clancy, 252-940-0981
Email Contact
Joe Fowler, 408-410-2451
Email Contact




Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Editorial
More Editorial  
Jobs
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Verification Engineer for Ambarella at Santa Clara, CA
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
ASIC Design Engineer for Ambarella at Santa Clara, CA
Engr, Elec Des 2 for KLA-Tencor at Milpitas, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy