Extreme DA Granted Patent for Statistical Timing Optimization of Digital Circuits

Santa Clara, Calif. –– March 9, 2009 –– Extreme DA™, the leader in new-generation timing analysis software, announced it has been issued a patent by the United States Patent and Trademark Office for its method of statistical timing optimization of digital circuits.  The patent, #7,487,486, covers technology used for improvement of design performance and reduction in power consumption and die-size of digital IC designs produced in 65nm processes and below.

As IC technologies are scaled to finer feature sizes, it becomes increasingly difficult to control process and parameter variations. The increasing fluctuations in manufacturing processes cause uncertainties in circuit behavior, and significantly impact the circuit performance and product yield. The problem is made worse by the growing sensitivity of current designs to environmental fluctuations, such as variations in temperature and voltage supply. Current design methodologies fail to address the nanometer-scale manufacturing and design realities; specifically, how to consider large-scale variations at all levels of the design creation hierarchy.

In nominal timing analysis, critical path and slack are two important concepts that have been widely utilized for timing optimization, but the impact of large-scale process variations renders these concepts obsolete and invalid.  The method of this new patent addresses the critical need for a new methodology for using statistical timing analysis results to guide timing optimization, as well as to explore the tradeoff between performance, power consumption, yield and cost. 

"This patent forms the basis for a new innovative approach to statistical timing analysis," said Mustafa Celik, CEO. "It describes the next-generation capability needed for the complex nanometer designs which chipmakers face today. For leading-edge digital ASIC designers, they can no longer rely on traditional timing validation methods to improve designs.  We believe our innovative statistical timing analysis in GoldTime delivers a new level of accuracy and robustness for optimizing ICs performance and yield."

About GoldTime — The New Standard in Sign-off Timing
GoldTime by Extreme DA, is the new-generation timing analysis technology that delivers 5X better speed and capacity. With its new from-the-ground-up architecture, designers can sign-off with certainty and achieve faster timing closure. Whether verifying a current generation design across corners or doing a statistical analysis to optimize the performance, power and yield for 40nm ICs, GoldTime delivers the answers while the competition is still figuring out the results.

About Extreme DA
Headquartered in Santa Clara, Calif., venture-funded Extreme DA develops and licenses software products that provide sign-off analysis and improve the performance and yield of nanometer integrated circuits prior to manufacture.  The company’s investors include Foundation Capital, IT-Farm Corporation, and Lanza techVentures.  For the latest news and information on Extreme DA, visit www.extreme-da.com or write to info@extreme-da.com.


Extreme DA, the Extreme DA logo, and Extreme DA GoldTime are trademarks of Extreme DA.  All other legal marks are the property of their respective owners.

Contact :
Jean Armstrong, PR Counsel for Extreme DA        Ruben Molina, Dir. of Technical Marketing
Armstrong and Associates, Inc.                   Extreme DA
jean@aaa-pr.com,  503-477-5434                   408-588-1112, x.32

Review Article Be the first to review this article

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Staff Software Engineer - (170059) for brocade at San Jose, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Upcoming Events
EDI CON China 2017! at Shanghai Convention & Exhibition Center of International Sourcing (SHCEC) No.2739 West Guangfu Road Putuo District, Shanghai (200062) China - Apr 25 - 27, 2017
2017 SEMICON Southeast Asia at SPICE Arena Penang Malaysia - Apr 25 - 27, 2017
2017 IoT Developers Conference at Santa Clara Convention Center California - Apr 26 - 27, 2017
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy