Jasper Design Automation’s JasperGold Is a Finalist in EDN’s 19th Annual Innovations Award Competition

MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—February 11, 2009— Jasper Design Automation, provider of advanced formal technology solutions, today announced that its flagship product, JasperGold® Verification System, has been selected from among hundreds of nominations as a finalist for this year’s EDN Innovation Awards under the category of ‘EDA: Design Analysis.’ A breakthrough in formal verification technology, JasperGold delivers exhaustive confidence across designer-level blocks, addressing the need for high RTL reliability. Unlike formal tools focused on implementation-level assertion-based verification, JasperGold raises the level of formal verification to end-to-end specification-level properties, delivering the highest design confidence possible today. The benefits of this production-proven formal technology solution span the complete SoC design cycle. System architects, logic designers, verification engineers and silicon bring-up teams can design, explore and debug RTL, ensure correctness of block-level functionality, and perform rapid post-silicon validation and debug.

Instituted in 1990, the Innovation Awards honor the people, products, and technologies that have shaped the semiconductor industry over the past year. During the month of February, EDN’s worldwide audience of electronic engineers and engineering managers will be invited to vote online to select the ultimate winners from among the finalists. Jasper encourages you to visit: www.EDN.com/innovation19 to place your vote for JasperGold. The winners will be announced at a dinner and awards ceremony on March 30, 2009, in San Jose, California.

“Hundreds of nominations were examined in preparation for EDN’s 2008 Innovation Award program,” said Rick Nelson, EDN editor-in-chief. “In our February 5th print issue, as well as online at edn.com, we present 94 finalists that are strong candidates across 26 product categories. Jasper’s JasperGold Verification System is one of the strong contenders in the ‘EDA: Design Analysis’ category because it delivers formal verification technology while addressing production issues and the complete SoC design cycle.”

JasperGold is unique from other formal verification solutions in that it conquers capacity issues with automatic counter abstraction, Formal Scoreboard™, Proof Accelerators™, patented Design Tunneling™ and interactive proof capabilities. Secondly, it offers design visibility enabled by Jasper’s patented visualization technology. Lastly, JasperGold’s powerful methodology, along with Jasper’s consultative “Targeted ROI” approach, enables customers to conquer their top verification challenges, mitigating project risks while reducing schedules and development costs.

“Jasper is delighted to have JasperGold selected as a finalist from among the submissions of many highly respected design analysis solutions,” said Kathryn Kranen, president and CEO of Jasper Design Automation. “Our customers tell us that they are using JasperGold to decrease the design verification burden throughout the chip development flow, and that it is providing them with greater design confidence, improved schedule predictability and greater design quality.”

About EDN and EDN.com

EDN serves the vital information needs of design engineers and engineering managers worldwide. EDN.com delivers a three-dimensional view of the electronic industry via news coverage, strategic business information, and in-depth technical content. ( www.edn.com). EDN is published by Reed Business Information ( www.reedbusiness.com/us).

About Jasper Design Automation

Jasper is a privately-held EDA software company leveraging formal technologies to deliver high value solutions for the design and verification of electronic systems and semiconductors. The company delivers products utilizing advanced formal analysis and Behavioral Indexing™ technologies to the global electronics market. Jasper is headquartered in Mountain View, California, and has offices and distributors located in North America, South America, Europe, and Japan. Visit Jasper online at http://jasper-da.com.

Jasper Design Automation, the Jasper Design Automation logo, ActiveDesign, Behavioral Indexing, Activated Design, and JasperGold are trademarks or registered trademarks of Jasper Design Automation, Inc. All other trademarks mentioned are the property of their respective companies.


For Jasper Design Automation
Francine Bacchini, +1-408-267-6602
Email Contact

Review Article Be the first to review this article
Featured Video
More Editorial  
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Test Development Engineer(Job Number: 17001697) for Global Foundaries at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
Technical Support Engineer Germany/UK for EDA Careers at San Jose, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy