Calypto to Present at Low-Power Design Summit

SANTA CLARA, Calif.—(BUSINESS WIRE)—September 30, 2008— Calypto Design Systems Inc., the leader in sequential analysis technology, will present at the one-day Low-Power Design Summit Wednesday, October 1, hosted by the Power Forward Initiative. The technical event will be held at Cadence Design Systems Pebble Beach Conference Room in Building 5 in San Jose, Calif.


Anmol Mathur, Calyptos chief technology officer and founder, will present, Sequential Transformations for Low Power, during Track 4: Architectural low-power trade-off techniques. The session begins at 1:30 p.m.

The event is free and open to hardware engineers working on or considering low-power design techniques. Attendees will hear from low-power experts, such as Dr. Mathur, about best practices and proven capabilities that can be adopted to design low-power wireless and wired electronics.

For more details on Calypto, go to:

To learn more on the Low-Power Design Summit, visit:

About Calypto

Founded in 2002, Calypto Design Systems, Inc. empowers designers to create high-quality, low-power electronic systems by providing best-in-class power optimization and functional verification software, based on its patented sequential analysis technology. Calypto, whose customers include Fortune 500 companies worldwide , is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. More information can be found at:

Calypto, PowerPro, SLEC and Enabling ESL are trademarks of Calypto Design Systems Inc. All other trademarks are property of their respective owners.


Public Relations for Calypto Design Systems
Nanette Collins, 617-437-1822
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