Mentor Graphics Provides Advanced Design For Manufacturing Capabilities in TSMC Reference Flow 9.0

WILSONVILLE, Ore.—(BUSINESS WIRE)—June 12, 2008— Mentor Graphics Corporation (Nasdaq:MENT) today announced that Mentors place-and-route, physical verification, design-for-manufacturing (DFM) and design-for-test (DFT) tools can be accessed through Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) Reference Flow 9.0.

Mentor Graphics continues to address the growing challenges of advanced IC design and manufacturing, said S.T. Juang, senior director of design infrastructure marketing at TSMC.

TSMC Reference Flow 9.0 accesses Mentor capabilities in the following areas:

  • New DFM implementation capabilities for hierarchical critical area analysis (CAA), hierarchical chemical-mechanical polishing (CMP), concurrent CAA optimization
  • Hierarchical DFM analysis for all three physical DFM defects: lithography process checking (LPC), CMP and CAA
  • Electrical DFM improvements including Table-Based DFM-LPE (advanced device parameter) extraction, and Thickness-to-Electrical (T2E) silicon-based models
  • CMP support for E-Hotspots and intelligent metal fill with model- and density-based modes
  • DFT solutions addressing bridge defects with N-detection algorithms, and a layout viewer to show the physical location of defects
  • Memory built-in self-test (BIST) support for TSMC electrical fuse intellectual property (IP) for single-insertion embedded memory repair

Our continued collaboration with TSMC is solving some of the biggest challenges for customers working at leading-edge process nodes, said Joe Sawicki, vice president and general manager, Design to Silicon Division, Mentor Graphics. Our close cooperation under TSMCs Active Accuracy Assurance initiative means that Mentor design-to-silicon flows accurately reflect TSMCs advanced manufacturing processes.

Mentors Olympus-SoC system provides new capabilities for hierarchical CAA, hierarchical VCMP and concurrent CAA optimization. Using a variety of enhancement techniques such as cell swapping, via reduction, via doubling, expand enclosure, and wire spreading/widening, all within a timing analysis context, the Olympus-SoC system improves yield while ensuring rapid timing closure. The Olympus-SoC product also takes into consideration the density maps of cell libraries and macros during fill insertion for a more uniform fill.

The Calibre CMPAnalyzer model-based CMP solution, which has been certified since RF7.0 and extended with SmartFill in RF8.0, now supports T2E and E-Hotspots functionality. This provides thickness values at a higher resolution for CMP analysis, allowing both functional and electrical planarity analysis and control, and can drive more accurate parasitic extraction using the Calibre xRC product. Additionally, Calibre the nmLVS product has been enhanced to incorporate TSMCs Table-Based DFM-LPE requirements for executing advanced device parameter extraction to account for silicon stress effects and provide the most accurate representation of manufactured devices.

The Calibre® YieldAnalyzer solution adds to Reference Flow 7.0 and 8.0 certification with hierarchical CAA for Reference Flow 9.0. It can characterize standard cells in terms of expected yield, and can be used with the Calibre YieldEnhancer tool for interactive IP fixing based on Critical Feature Analysis using recommended rules. The Calibre YieldAnalyzer product can also be used in a flow with the Olympus-SoC system by providing cell library yield assessment data, which the Olympus-SoC tool uses for cell selection. TSMC customers now have a complete solution for reducing random defects.

The Calibre LFD solution has been qualified for RF 9.0 as well as TSMCs 4N40 processes for all layers, and now includes hierarchical LPC features for faster turn around time.

DFT capabilities based on the industry-leading TestKompress® scan test tool, MBISTArchitect, and YieldAssist products, which have been part of TSMCs reference flow since release 6.0, continue to include logic and memory testing, power reporting during automatic test program generation (ATPG) for addressing test-specific power issues, and timing-aware ATPG features for targeting small delay defects. In RF 9.0, the TestKompress product adds the ability to target bridge defects using N-detection algorithms. Mentors MBISTArchitect tool now provides support for TSMC embedded memories using the TSMC electrical fuse IP to enable single-insertion embedded memory repair during testing. Also, failure diagnostic capabilities have been enhanced by integrating the Mentor YieldAssist tool with the Calibre Layout Viewer to provide a physical layout view of defect areas.

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $850 million and employs approximately 4,200 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: .

1 | 2  Next Page »

Review Article Be the first to review this article
Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Job Openings: Can EDA Predict the Future
More Editorial  
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Technical Support Engineer Germany/UK for EDA Careers at San Jose, CA
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy