New API Standard Opens SystemC to Pre-Silicon Embedded Software Development and Virtual Platform Model Interoperability
"We recognize the need for system-level solutions that improve the efficiency of pre-silicon software development as well as complete system verification, and interoperable models are key," said Takashi Hasegawa, director, ESL & Verification Department, SoC Design Engineering Division of Fujitsu Microelectronics Limited. "The TLM-2.0 compliant SystemC models delivered in Synopsys' DesignWare System-Level Library are a valuable piece of an ESL design methodology enabling the rapid development of virtual platforms."
Virtual platforms built in Synopsys' Innovator are fast, fully functional simulation models of hardware that enable development and integration of software months before hardware is available. More than 50 commercial platforms developed in Synopsys' Innovator are being used by embedded software developers today. SystemC TLM-2.0 compliant transaction-level models are the basic building blocks required to build virtual platforms for early software development, hardware/software co-design, architectural exploration and system verification. The DesignWare System-Level Library is the industry's most comprehensive portfolio of tool-independent, standards-based TLMs, and its models can be used in any SystemC TLM-2.0 compliant simulator.
"Model interoperability across simulators protects the designer's investment in TLM-2.0 models," said Mike Meredith, president of OSCI. "The newly ratified capabilities of the TLM-2.0 standard enable simulation performance previously seen only in proprietary solutions and mark the removal of an important obstacle for widespread adoption of SystemC-based virtual platforms for pre-silicon embedded software development."
The OSCI SystemC TLM-2.0 standardization has been focused at fulfilling the key user requirements of increased performance, flexibility and interoperability. Synopsys was an active participant in the development of the standard in order to ensure that it addresses the need for a high-performance interface standard. The company's efforts in the working group have included development work on the proof-of-concept implementation, examples and collateral material.
"In our 2007 ESL Market Trend Report, we predicted more rapid growth for virtual platforms once the standards issues get resolved," said Gary Smith, president of Gary Smith EDA. "Standardization of TLM-2.0 removes an important hurdle for virtual prototyping to enter mainstream adoption and to more closely link embedded software and hardware development."
Synopsys will showcase the TLM-2.0 compliant DesignWare System-Level Library and the Innovator virtual platform development tools featuring TLM-2.0 compliant component authoring and component import at the Design Automation Conference in Anaheim (June 9 - 12, 2008 in booth #1349).
"The roll-out of our SystemC TLM-2.0 compliant commercial tool and library offerings marks an important milestone for our users, and we believe that we are the first to offer a TLM-2.0 compliant tool and library," said John Koeter, senior director of marketing for IP and Services at Synopsys. "Openness and interoperability are the key triggers for SystemC-based virtual platforms to finally move from early adoption of proprietary solutions into broad mainstream adoption."
TLM-2.0 compliant versions of the DesignWare System-Level Library and Synopsys Innovator currently expected to be available in Q3 2008. For more information, see http://www.synopsys.com/virtualplatform and http://www.designware.com/sll.
About DesignWare IP
Synopsys offers a broad portfolio of high-quality, silicon-proven digital, mixed-signal and verification IP for system-on-chip designs. As a leading provider of connectivity IP, Synopsys delivers the industry's most comprehensive solutions for widely used protocols such as USB, PCI Express, SATA, Ethernet and DDR. In addition to connectivity IP, Synopsys offers SystemC transaction level models to build virtual platforms for rapid, pre-silicon development of software. When combined with a robust IP development methodology, extensive investment in quality and comprehensive technical support, DesignWare IP enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit http://www.synopsys.com/designware
Synopsys, Inc. (NASDAQ: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.
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Editorial Contacts: Sheryl Gulizia Synopsys, Inc. 650-584-8635 firstname.lastname@example.org Ellen Van Etten MCA 970-778-6094 email@example.com