Verification Expert Presenters Include JL Gray, Brian Bailey and Cliff Cummings
Real Intent, Inc., the leading supplier of formal verification software for electronic design, is hosting a Verification Experts’ Corner with presentations by JL Gray, Brian Bailey and Cliff Cummings at the Design Automation Conference (DAC).
Verification Experts’ Corner
Booth # 2540
Anaheim Convention Center, Anaheim, California
Monday, June 9, 11am, JL Gray, Verilab & Author Cool Verification Blog
Topic: Santa Claus, the Tooth Fairy and SystemVerilog Interoperability
Tuesday, June 10,11am, Brian Bailey, Brian Bailey Consulting
Topic: The Myths and Legends of Functional Verification
Wednesday, June 11,11am, Cliff Cummings, Sunburst Design
Topic: Design and Verification of Asynchronous Clock Crossings in a SystemVerilog World
More about the Verification Experts’ Corner Presentations
Santa Claus, the Tooth Fairy and SystemVerilog Interoperability
JL Gray, Verilab & Author Cool Verification Blog
SystemVerilog today purports to be the one common verification language supported by all tool vendors. However, in an interesting parallel to the situation a decade ago, verification IP from different sources is likely to be incompatible due to differences in the SystemVerilog language and methodology support between various Electronic Design Automation (EDA) vendors. As with its close cousins Santa Claus and the Tooth Fairy, the reality is that (spoiler alert) SystemVerilog Interoperability is a myth. This presentation also includes a discussion of the likelihood SystemVerilog interoperability will move from myth to reality as a result of the efforts of Accellera’s Verification Intellectual Property (VIP) Technical Subcommittee (TSC).
The Myths and Legends of Functional Verification
Brian Bailey, Brian Bailey Consulting
While the industry changes around us, how often do we re-examine some of the fundamental issues that led us to certain decisions? The world of verification is one such area where many myths and legends have developed over time and some of them deserve to be exposed. This fun and provocative presentation looks at three such myths and how they could affect the way in which future methodologies are put together.
Design and Verification of Asynchronous Clock Crossings in a SystemVerilog World
Cliff Cummings, Sunburst Design
Within a single clock domain, design for timing closure requires only an understanding of path delays, setup and hold on registers, clock skew, and an accurate static timing analysis tool. Once the problem expands to include multiple asynchronous clock domains, this methodology completely breaks down. Cliff will present the design techniques required to ensure reliable cross domain data transfers. He will describe the proven techniques and the newest information relative to this topic. He will discuss how Clock Design Crossing (CDC) methodology and CDC verification solutions can create proven correct CDC designs.
Information and Registration:
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About Real Intent
Real Intent is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent’s products dramatically improve the functional verification efficiency of leading edge application specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses, including AMD, nVidia and NEC Electronics use Real Intent software.
Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, web: www.realintent.com, e-mail: Email Contact.
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