WHAT: eSilicon Corporation's Kalar Rajendiran will participate on a panel at the inaugural Intellectual Property Symposium, April 15, 2008 at the San Jose Fairmont Hotel. The event is a joint effort of EETimes, Semiconductor Insights and Portelligent, and will examine a number of business, technical and legal issues around the use of semiconductor IP in the development of complex chips. Mr. Rajendiran will join executives from Denali Software, Mentor Graphics and ST Microelectronics on the panel entitled "Silicon Subsystems: How to develop SoCs Faster and with Lower Risk." The panel will discuss what subsystems are and how they help successful SoC development. For more information on the IP Symposium, go to: http://www.eetimes.semiconductor.com/ WHEN: April 15-16, 2008 SoC Panel is Tuesday, April 15, 1:45-2:45 in the Hillsborough Room WHERE: Fairmont Hotel San Jose, California WHO: eSilicon, an industry-leading Value Chain Producer (VCP) for the semiconductor industry, provides a comprehensive suite of design, productization and manufacturing services, enabling a flexible, low-cost, lower-risk path to volume production. The company delivers chips to system OEMs and fabless semiconductor companies who serve a wide variety of markets including the consumer, computer, communications and industrial segments. For more information, visit www.esilicon.com
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