NOTICE - Implementing a Self-Running, Deterministic Verification System FREE Seminar

Aldec, Inc. is pleased to invite you, and your design team to our ABSOLUTELY FREE Technical Web Seminar! The topic: Implementing a Self-Running, Deterministic Verification System. Please review the below seminar summary information. Seminars fill up fast so don’t delay in registering today!

CLICK HERE TO REGISTER
Schedule: Schedule: Thursday March 27, 2008, 11:00 AM - 12:00 PM, Pacific Daylight Time
AVMS V-06 Seminar: Implementing a Self-Running, Deterministic Verification System.

Description: It is known that direct testing discovers only the bugs it is designed to test. In order to push beyond the limits of verification, we must bring a random factor to our test environment. We will show how to build an effective test architecture to support constrained random design testing. A special design monitor is required to alert the testbench to design errors, collect functional coverage data, and inform a stimulus generator of test completion. Transaction level testing will also be leveraged to keep the verification at the high level of abstraction, and to increase both design and test reuse.

Agenda:

  • Transaction level testing: driver and stimulus generator.
  • Building a design monitor with the PSL assertion language.
  • Randomizing the stimulus generator. Using SystemC Verification Library (SCV) for constraint solving.
  • A practical design example in operation.

For More About Aldec®
www.aldec.com

After registration, you will receive login information by email prior to the event. We hope you and your colleagues will attend.

Marcom Team
Aldec, Inc.
Tel: +1 702 990 4400

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