"Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test"
The patented invention are methods and apparatus for providing ordered capture clocks, each running at its intended speed, to detect or locate faults within each clock domain and faults across clock domains in an integrated circuit in scan ATPG test mode, where each domain has scan chains. Dubbed "staggered launch-on-capture" or "staggered double-capture", the capture-clocking scheme allows designs containing synchronous and asynchronous clock domains to perform at-speed scan ATPG test. SynTest TurboScan and VirtualScan test compression products are based on this technology invention. A slow Scan-Enable control signal, commonly used for slow-speed test, is also used for at-speed scan testing using this patented invention. Use of this patented invention results in improved productivity and time-to-market (TTM). Since without it, only "one-hot" clock method can be used for at-speed scan testing resulting in significant increase in test application time on ATE (proportional to number of clock domains in the design) and subsequent significant increase in overall test cost.
SynTest Technologies, Inc., established in 1990, develops IP for advanced design-for-test (DFT) and design-for-debug/diagnosis (DFD) applications and markets them throughout the world, to semiconductor companies, system houses and design service providers. The company has filed more than 38 US/PCT patents of which 13 have been issued and 2 allowed. The Company's products improve an electronic design's quality and reduce overall design and test costs. Various applications that use these IP (intellectual properties) include logic BIST, memory BIST, boundary-scan synthesis, Scan/ATPG with test compression, concurrent fault simulation, silicon debug and diagnosis. The company headquartered in Sunnyvale, California, has offices in Taiwan, Japan, Korea and China, and distributors in Europe and Asia including Israel. More information is available at www.syntest.com.
SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave., Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956, E-Mail: Email Contact
SynTest and TurboBIST-Logic are trademarks of SynTest Technologies, Inc. All other trademarks are property of their respective owners.
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ATPG: Automatic Test Pattern Generation
ATE: Automatic Test Equipment
BIST: Built-In Self-Test
IP: Intellectual Property