Implementing Low-Power Configurable Processors - Practical Options and Tradeoffs - Technical Paper from DAC 2005

Tensilica

Paper by John Wei and Chris Rowen.

Configurable processors enable dramatic gains in energy efficiency, relative to traditional fixed instruction-set processors. This energy advantage comes from three improvements. First, configuration of the instruction set permits a much closer fit of the processor to the target applications, reducing the number of execution cycles required. Second, configuring the processor removes unneeded features, reducing power and area overhead. Third, automatic processor generation tools enable logic optimization, signal switching reductions, and seamless mapping into low-voltage circuits and processes, for very low-power operation. The first improvement has been well-studied. Analysis of the second and third improvements requires detailed circuit and layout experiments, which is the primary focus of this paper.

Starting from a range of existing available power saving options, this work explores the tradeoff and analyzes the results: the design priority tradeoff, the process technology impact, and implementing low-power configurable processor using commercial scaled-VDD cell libraries compatible with mainstream SOC practices. These real processor designs can achieve power dissipation approaching 20µW/MHz at 0.8V and close to 10µW/MHz at 0.6V, using production 0.13um libraries. Finally, this work quantifies the dramatic process, voltage and temperature dependence in post-layout leakage power for small processor designs.


Read the complete story ...
Rating:


Review Article Be the first to review this article
Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Job Openings: Can EDA Predict the Future
More Editorial  
Jobs
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Verification Engineer for Ambarella at Santa Clara, CA
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Test Development Engineer(Job Number: 17001697) for Global Foundaries at Santa Clara, CA
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy