Communications Leader Uses Synopsys' Tools and Flows From Design Through Physical Implementation
"Marvell has been a longtime user of Synopsys' design and verification technology and uses key tools such as Design Compiler(R), Astro(TM), PrimeTime(R) and VCS(R) to get our high-performance products to market," said Pantas Sutardja, chief technical officer at Marvell. "We use Design Compiler and Astro as our primary synthesis and place-and-route solution. Adding Synopsys' Astro-Rail(TM), DFT MAX, JupiterXT(TM) and Physical Compiler(R) technology has further strengthened our flow and improved our time to results."
Marvell's design implementation suite includes Synopsys' Galaxy products including Design Compiler RTL synthesis solution, JupiterXT physical planning solution, Physical Compiler and Astro physical implementation solution, DFT MAX 1-pass test synthesis solution, Power Compiler(TM) power management solution, Astro-Rail power rail analysis solution, Astro-Xtalk(TM) cross-talk analysis solution, PrimeTime static timing sign-off solution, Star-RCXT(TM) parasitic extraction solution, and TetraMAX(R) automatic test generation (ATPG) solution. Additionally, Marvell uses Synopsys', VCS RTL verification solution and Vera(R) testbench automation.
"To see an industry leader like Marvell using our solutions for their high-performance, complex system-on-chip and networking products is truly gratifying," said Antun Domic, senior vice president and general manager of the Implementation Group at Synopsys. "Marvell and Synopsys have enjoyed a strong history of collaboration. In fact, Marvell was a key partner in the development of our power network synthesis technology -- part of our JupiterXT solution. We look forward to continued mutual success."
Synopsys, Inc. is a world leader in EDA software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http:/ www.synopsys.com.
NOTE: Synopsys, Design Compiler, Physical Compiler, PrimeTime, TetraMAX, VCS and Vera are registered trademarks of Synopsys, Inc. Astro, Astro-Xtalk, Astro-Rail, Galaxy, JupiterXT, Power Compiler, and Star-RCXT are trademarks of Synopsys. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Editorial Contacts: Carole Murchison Synopsys, Inc. 650-584-4632 Email Contact Stephanie Mrus Edelman 650-968-4033 Email Contact
Web site: http://www.synopsys.com//