Esterel Technologies Adds Top-Level Validation Capabilities and Fast-C Code Generator to Newest Release of Esterel Studio

MOUNTAIN VIEW, Calif. and GUYANCOURT, France--(BUSINESS WIRE)--March 4, 2002--

New Features Help System-Level Designers Master the

Complexity of IP Integration for System-on-Chip Designs;

Help Telecom Protocol Designers Develop Accurate, Fast,

and Portable C Code

Esterel Technologies today announced the newest release of Esterel Studio(TM), with support from customers Texas Instruments, ST Microelectronics and France Telecom R&D.

Esterel Studio is a software product used by designers of system-on-chip (SoC) for system-level functional verification and by developers of embedded software to create telecommunications protocols ready to embed in telecommunications equipment.

Esterel Studio 3.1.6, the new release, adds two major capabilities: system-level transition coverage and a Fast-C code generator. In addition, the new release provides access to external text editors and dynamic waveform display during simulation.

The new version of Esterel Studio gives designers the ability to measure 100 percent of the states a design can reach, and 100 percent of the transitions between states, to fully analyze the global interactions among all the IP blocks on a chip. Transition coverage is very important for SoC designs that integrate numerous intellectual property (IP) blocks, due to the vast numbers of possible transitions between the blocks.

Other verification tools use predetermined test sets to measure state and transition coverage of individual components of a design at the RTL or gate level. The Esterel advantage is that Esterel Studio automatically generates the test sets, works at the system level and tests all concurrent interactions of the components integrated together.

The new Fast-C Code Generator is especially useful for developers of embedded telecommunications protocols who need accurate, fast, portable code they can import directly into their products. Without Fast-C Code Generator, telecom protocol developers must hand-code the programs, which is a time-consuming and error-prone task.

A new approach to top-level validation to enhance and automate verification of SoC designs

Esterel Studio automates the functional verification of SoC designs, enabling designers to describe IP blocks and automatically generate exhaustive and non-redundant testbench scenarios to verify the interoperability of the blocks.

Transition coverage increases a designer's confidence that an SoC design will function properly. Transition coverage is a set of tests performed on a design to ensure that each state can be reached from every other state. While state coverage -- included in the previous release of Esterel Studio -- enables SoC designers to generate all possible reachable states of the SoC, transition coverage generates all the transitions from one state to another. If one or more states or transitions are not tested, malfunctions that exist in a design could go undetected until a product reaches the consumer. And this may result in the loss of millions of dollars.

"It's unrealistic to manually or randomly calculate all the states and transitions in a SoC design," said Hassan Laasri, vice president of marketing at Esterel Technologies, "and even directed random approaches often don't get close enough. Only through structured methods such as those in our underlying technology can we provide 100 percent state and transition coverage.

"A structured, formal approach to defining the transactions provides a clean spec," added Laasri. "We can guarantee 100 percent coverage of the behavior, and define a model of interaction between the IP blocks to get that coverage. Without Esterel Studio, designers doing complex SoC designs or module integration are spending far too much time running tests without knowing what they are measuring."

About Esterel Technologies

Esterel Technologies provides electronic system and embedded software designers with methodologies and tools that improve their productivity and remove the barriers between system specification, implementation, and validation. The company's products automate costly and time-consuming coding and validation work through executable specification, intelligent testbench generation and automatic code generation. Esterel Technologies is an international company with offices in France, Germany, U.K., and the United States.

For more information: www.esterel-technologies.com.


Contact:
     Esterel Technologies
     Hassan Laasri, +33 (0)1-30-12-27-42
     
Email Contact
       or
     Cayenne Communication
     Michelle Clancy, 252/940-0981
     
Email Contact



Review Article Be the first to review this article

Aldec Simulator Evaluate Now

Featured Video
Jobs
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
Senior Formal FAE Location OPEN for EDA Careers at San Jose or Anywhere, CA
DSP Tools Engineer for Cirrus Logic, Inc. at Austin, TX
Design Verification Engineer for Cirrus Logic, Inc. at Austin, TX
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
Upcoming Events
IC Open Innovation Panel During REUSE 2017 at Santa Clara Convention Center 5001 Great America Parkway Santa Clara CA - Dec 14, 2017
Essentials of Electronic Technology: A Crash Course at Columbia MD - Jan 16 - 18, 2018
Essentials of Digital Technology at MD - Feb 13 - 14, 2018
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise