Imperas Virtual Platform Based Software Tools at DAC 2017

Virtual Prototyping in Demonstrations of Software Development Using Continuous Integration and Jenkins, Debug and Test, and a Tutorial on Linux Bring Up on Heterogeneous Multiprocessor SoCs

OXFORD, England — (BUSINESS WIRE) — May 22, 2017Imperas Software Ltd., the leader in high-performance software simulation, today announced their participation at the Design Automation Conference (DAC) 2017, inviting developers of electronic products to register for a demonstration of Imperas virtual platforms for embedded software and systems development, debug and test at the Imperas booth in the World of IoT pavilion, booth #521.

DEMO HIGHLIGHTS: See Imperas virtual platform-based solutions for embedded software development, debug, analysis, and verification demos in the World of IoT pavilion, booth #521.

  • Imperas demos will show a wide variety of Open Virtual Platforms (OVP) models and virtual prototypes, with processor models of ARM (Cortex-A, M and R families), Altera, ARC, Imagination Technologies (MIPS), Renesas, RISC-V and Xilinx cores.
  • These demos will showcase the Imperas software Verification, Analysis and Profiling (VAP) tools, including OS-aware tools, plus heterogeneous multiprocessor/multicore debugging capabilities.
  • Imperas will show virtual platforms in a Continuous Integration / Continuous Test embedded software development environment using Jenkins, resulting in an efficient methodology to develop high-quality software.

TUTORIAL: Linux Bring Up on Heterogeneous Multiprocessor SoCs

  • Heterogeneous multiprocessor SoCs are common in applications such as advanced driver assistance systems (ADAS) and autonomous vehicles, networking, industrial automation, security, video analytics and machine learning. These SoCs often have multiple homogeneous or heterogeneous clusters of CPUs, GPUs, and/or hardware accelerator units that work together on a common set of data. Linux, the general purpose operating system of choice for embedded systems, must be modified for these heterogeneous multi-cluster architectures to support coherence between clusters, as well as differences such as number of processors, processor type, and other features. Vendors often use an open source Linux distribution, then customize for the specific SoC, including drivers for the peripherals, other customizations and unique features. Obviously, this gets quite complex, and the need to port, customize and bring up Linux on these heterogeneous SoCs requires significant engineering effort. So how can developers be more efficient? What are the best practices for Linux porting and bring up on heterogeneous multi-cluster/multiprocessor SoCs?
  • John Min, Solution Engineer at Imagination Technologies, covers components of the basic Linux kernel, device trees and other customizations, SMP variations, static and dynamic drivers, and coherency for multi-cluster architectures. The methodology used for bring up of the Linux kernel, starting with boot loaders including U-boot, on hardware is presented.
  • Simon Davidmann, CEO of Imperas Software, discusses a robust debug and test environment based on virtual platform technology. Virtual platforms provide a complementary approach to porting and bring-up on hardware, with benefits of controllability, observability and repeatability. Virtual platforms also enable easy automation of testing, as needed for an Agile Continuous Integration (CI) development and test methodology. Specific OS-aware tools are also highlighted, plus non-intrusive memory monitors, the use of software assertions, and code and functional coverage techniques for operating systems and drivers.

WHEN AND WHERE: DAC 2017 is June 18-22 at the Austin Convention Center, Austin, Texas.

  • Exhibits are open June 19-21.
  • Imperas tutorial is Monday, June 19 from 10:30am- 12:00pm in room 17AB.

For more information, or to set up meetings with Imperas at DAC, please email Email Contact

About Imperas

For more information about Imperas, please see www.imperas.com.

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.



Contact:

Imperas Software Ltd.
Larry Lapides, 925-519-1234
Email Contact

 




Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Field Application Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
CST: Webinar series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise