AMAZING IMPROVEMENT OF POWER AND DENSITY FOR RFID CHIPS WITH STANDARD CELL LIBRARIES AT 180 NM

September 26, 2016 - Grenoble, France - For RFID Tags, dynamic power is a critical factor as the capability for lower power translates immediately into a wider range of detection (RFID tag read range) and/or a highest identification rate in the same range.

The main degree of freedom to improve power and area of RFID tag is located in the digital block.

The  SESAME eLC standard cell library enables up to 50% savings of dynamic power when compared to any other logic library available at 180 nm. Such a comparison must be based on the  Motu uta v6.0 benchmark with its Tsunami testbench (see results below), providing a quick and simple way to the expected improvement of overall performances of RFID tags.

Figure 1: SESAME eLC versus a free library - Dynamic power comparison at TSMC 180 nm G

Standard cell optimization

Post-synthesis results, based on Motu-Uta V6 RTL benchmark – worst case conditions (SS 1.62 V 125°C )

Conversely, if area saving is more critical,  SESAME uHD library represents the best trade-off between high density and low power consumption. This library, which proudly claims to be the densest library available at 180nm, enables up to 25% area reduction (see figure below). For RFID chip dominated by its digital area, the overall area saving represents the decisive incentive to opt for SESAME uHD library.

Figure 2: SESAME uHD versus free library - Silicon area comparison at TSMC 180 nm G

Standard cell optimization

Post-synthesis results, based on Motu-Uta V6 RTL benchmark – worst case conditions (SS 1.62 V 125°C )

I want more information about your standard cell libraries at 180 nm




Review Article Be the first to review this article
Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Fall Schedule: A Host of Must-attends
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Senior Methodology Automation Engineer for EDA Careers at San Jose, CA
DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA
Proposal Support Coordinator for Keystone Aerial Surveys at Philadelphia, PA
Upcoming Events
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
The Rise of Mechatronics at Dassault Systèmes San Diego 5005 Wateridge Vista Drive San Diego CA - Sep 12, 2017
The Rise of Mechatronics at Buca di Beppo - Pasadena 80 West Green Street Pasadena CA - Sep 13, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy