Cadence Delivers Integrated System Design Solution for TSMC InFO Packaging Technology

Companies collaborated to enable implementation, signoff and electro-thermal analysis tools to support customer designs using InFO packaging

SAN JOSE, Calif., Sept. 21, 2016 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the immediate availability of an integrated system design solution for TSMC's advanced wafer-level Integrated Fan-Out (InFO) packaging technology, resulting from a collaboration between Cadence and TSMC that was announced earlier this year. Cadence is now offering implementation, signoff and electro-thermal analysis tools that enable concurrent multi-chip optimization for designs that incorporate InFO.

Cadence Logo.

For more information on the Cadence® solution for TSMC's InFO technology, please visit

The Cadence solution includes:

  • Cadence System-in-Package (SiP): Provides the InFO design and layout platform with enhanced features to generate the complete layout of the system, in-design design rule checking (DRC), and IC-level physical signoff.
  • Multiple extraction solutions at the chip and package level: The Quantus QRC Extraction Solution and Allegro®-Sigrity Package Assessment and Extraction Option are specifically tailored for verifying InFO applications.
  • Multiple IC signoff solutions: The Tempus Timing Signoff Solution provides cross-die/cross-InFO timing checks, the Voltus-Sigrity Package Analysis offers multi-die concurrent electro-migration IR drop (EMIR) analysis, and the Cadence Physical Verification System (PVS) provides DRC and layout versus schematic (LVS) checking for InFO systems and heterogeneous dice.
  • Sigrity IC package analysis and 3D modeling: Enables layer-based thermal, electro-magnetic interference (EMI), static and dynamic IR analysis, and a thermal-aware EM multi-die InFO system.

"The new flow provides customers with an unparalleled, holistic IC and packaging solution that covers the full spectrum of heterogeneous, multi-chip designs in InFO technology," said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. "By working closely with TSMC, we are enabling our mutual mobile and IoT customers to further shorten system design and verification cycle times so they can get to market faster."

"We've seen continued demand for our InFO packaging technology because designers have the ability to integrate multiple chips into a single package while increasing design performance," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Through our ongoing collaboration with Cadence, we're bringing expanded capabilities to our customers so they can boost productivity and overcome competitive market pressures."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
Email Contact

Logo -


To view the original version on PR Newswire, visit:

SOURCE Cadence Design Systems, Inc.

Cadence Design Systems, Inc.

Review Article Be the first to review this article

Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Applications Engineer for intersil at Palm Bay, Florida
Design Verification Engineer for intersil at Morrisville, North Carolina
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise