Avery Design Systems Scale-Out With NVMe over Fabrics Verification Solutions

TEWKSBURY, MA — (BUSINESS WIRE) — August 9, 2016 — Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of NVM Express over Fabrics 1.0 and NVM Express 1.2.1 extensions to its NVM-Xactor verification IP enabling verification of both NVMe over PCIe and NVMe over Fabrics designs.

NVM-Xactor is a complete verification solution for NVMe core and subsystem design. NVM-Xactor allows design and verification engineers to quickly and extensively test the functionality of NVMe controller designs targeting memory or message transports. The NVM-Xactor solution includes:

  • NVM host software BFM
  • NVM host and controller bus/fabric adaptor
  • Reference NVMe controller and adaptor
  • Producer-consumer scoreboard
  • Compliance testsuite
  • Comprehensive protocol checks
  • Protocol analyzer tracker
  • Functional coverage model
  • Works with any PCIe and AXI IP or VIP
  • Developed in Native SystemVerilog/UVM

“NVMe over Fabrics is an essential technology to scale-out NVMe storage connectivity using the simplicity and efficiency of an End-to-End NVMe model”, said Chris Browy, VP Sales and Marketing of Avery Design Systems. “Our industry leading NVM-Xactor now spans the spectrum of client to enterprise NVMe design applications”.

“CNEX Labs has effectively employed the Avery NVMe and PCIe VIP for the development of our semiconductor solutions. Using these models and compliance testsuites has helped us to achieve comprehensive, high quality verification for our ASIC designs”, said Justin Heindel, VP Product for CNEX. “The technical support has been excellent, and we look forward to using Avery VIP products on future NVMe designs.”

NVM-Xactor works in conjunction with various physical transport layers including Avery’s leading PCI-Xactor PCI Express and AMBA Verification IP solutions or other fabric interfaces such as Ethernet, Fibre Channel, or Infiniband to supply a complete NVMe subsystem verification environment. A NVM bus/fabric adaptor layer provides memory and RDMA transport access interface by the NVM host software BFM to the NVMe Controller via the full bus/fabric protocol or through a bypass mode yielding faster simulation performance for large data movement. A reference NVMe controller layer also supports core-level verification by emulating the NAND Flash backend subsystem.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, HMC, ONFI/Toggle, NVM Express, SCSI Express, SATA Express, eMMC, SD/SDIO, and CAN FD standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.



Contact:

For Avery Design Systems:
Chris Browy, 978-851-3627
Email Contact




Review Article Be the first to review this article

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Staff Software Engineer - (170059) for brocade at San Jose, CA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy