TEWKSBURY, MA — (BUSINESS WIRE) — August 9, 2016 — Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of NVM Express over Fabrics 1.0 and NVM Express 1.2.1 extensions to its NVM-Xactor verification IP enabling verification of both NVMe over PCIe and NVMe over Fabrics designs.
NVM-Xactor is a complete verification solution for NVMe core and subsystem design. NVM-Xactor allows design and verification engineers to quickly and extensively test the functionality of NVMe controller designs targeting memory or message transports. The NVM-Xactor solution includes:
- NVM host software BFM
- NVM host and controller bus/fabric adaptor
- Reference NVMe controller and adaptor
- Producer-consumer scoreboard
- Compliance testsuite
- Comprehensive protocol checks
- Protocol analyzer tracker
- Functional coverage model
- Works with any PCIe and AXI IP or VIP
- Developed in Native SystemVerilog/UVM
“NVMe over Fabrics is an essential technology to scale-out NVMe storage connectivity using the simplicity and efficiency of an End-to-End NVMe model”, said Chris Browy, VP Sales and Marketing of Avery Design Systems. “Our industry leading NVM-Xactor now spans the spectrum of client to enterprise NVMe design applications”.
“CNEX Labs has effectively employed the Avery NVMe and PCIe VIP for the development of our semiconductor solutions. Using these models and compliance testsuites has helped us to achieve comprehensive, high quality verification for our ASIC designs”, said Justin Heindel, VP Product for CNEX. “The technical support has been excellent, and we look forward to using Avery VIP products on future NVMe designs.”
NVM-Xactor works in conjunction with various physical transport layers including Avery’s leading PCI-Xactor PCI Express and AMBA Verification IP solutions or other fabric interfaces such as Ethernet, Fibre Channel, or Infiniband to supply a complete NVMe subsystem verification environment. A NVM bus/fabric adaptor layer provides memory and RDMA transport access interface by the NVM host software BFM to the NVMe Controller via the full bus/fabric protocol or through a bypass mode yielding faster simulation performance for large data movement. A reference NVMe controller layer also supports core-level verification by emulating the NAND Flash backend subsystem.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, HMC, ONFI/Toggle, NVM Express, SCSI Express, SATA Express, eMMC, SD/SDIO, and CAN FD standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
For Avery Design Systems:
Chris Browy, 978-851-3627