DVCon U.S. 2017 Announces Call for Extended Abstracts, Tutorials & Panels

Submission site is open; deadlines earlier than in the past

LOUISVILLE, Colo. — (BUSINESS WIRE) — July 26, 2016 — The 2017 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, is now accepting extended abstract, panel and tutorial proposals for its conference to be held February 27-March 2, 2017 at the DoubleTree Hotel in San Jose, California.

The primary focus of DVCon U.S. is on the application of languages, tools, methodologies and standards for the design and verification of SoCs, electronic systems and integrated circuits.

“DVCon U.S. continues to be the industry’s leading forum for practicing design and verification engineers, managers and EDA tool suppliers to share advances in and application of design automation technology,” stated Dennis Brophy, DVCon U.S. 2017 General Chair. “We look forward to a program full of engaging content in an atmosphere where presenters and attendees can share and discuss the very latest solutions to the most challenging issues impacting design productivity today.”

Extended abstracts are being solicited for presentations that are highly technical and reflect real-life experiences and emerging trends. Extended abstracts should be between 600-1200 words. Deadline for submissions is August 18, 2016, which is earlier than in years past. The earlier deadline has been established to give more time after final papers have been submitted for presenters to hone their oral presentations and ensure they are the best they can be. More information and guidelines can be found here. Submissions are encouraged, but not limited to, the following areas: Verification and validation; system-level design and verification; design and verification reuse and automation; low-power and mixed-signal design and verification; formal-based verification.

As in recent years, DVCon U.S. will host two focused panel discussions. Panel proposals that provoke lively and timely debate on topics of importance to the design and verification community, and are on a specific topic of interest to the community are encouraged. Suggested topics include: Experiences using design and/or verification IP for SoC development; design and verification sign-off and closure; power aware design and verification challenges; technical and logistical challenges of multi-site projects; experiences deploying a verification methodology library, especially the deployment of UVM; designing and/or verifying complex SoCs and FPGAs using multiple HDLs and/or HVLs in a design cycle. Deadline for panel proposals is October 7, 2017. More information and guidelines can be found here.

Tutorial submissions should be on topics that are current, have a high-level of interest and offer strong continuing educational content. Tutorial sponsors will have an opportunity to present material in half-day sessions to a targeted group of qualified engineers. Deadline for tutorial proposals is September 30, 2016. More information and guidelines can be found here.

About DVCon

DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. DVCon is sponsored by Accellera Systems Initiative, an industry consortium dedicated to the development and standardization of design and verification languages. DVCon currently has three conferences around the globe: DVCon U.S., DVCon India and DVCon Europe. Follow @dvcon on Twitter or to comment, please use #dvcon.


MP Associates, Inc.
Nannette Jordan, 303-530-4562
Email Contact
HighPointe Communications
Barbara Benjamin, 503-209-2323
Email Contact

Review Article Be the first to review this article
Featured Video
More Editorial  
Upcoming Events
MPSoc Forum 2017 - July 2 - 7, 2017, Les Tresoms Hotel, Annecy, France at Les Tresoms Hotel Annecy France - Jul 2 - 7, 2017
SEMICON West 2017 at Moscone Center San Francisco CA - Jul 11 - 13, 2017
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
DVCon India 2017, Sept 14 - 15, 2017 at The Leela Palace Bengalore India - Sep 14 - 15, 2017
Verific: SystemVerilog & VHDL Parsers

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy