QuickLogic Announces Production Availability of EOS S3 Sensor Processing Platform

SUNNYVALE, CA -- (Marketwired) -- Jun 08, 2016 -- QuickLogic Corporation (NASDAQ: QUIK) -

  • QuickLogic has completed its production qualification for the new EOS S3 ultra-low power sensor processing SoC
  • The EOS S3 SoC platform enables advanced sensor processing applications for smartphone, wearables & IoT applications with substantially lower power consumption than traditional MCU solutions
  • Initial tier-one customer shipments are scheduled for late June

QuickLogic Corporation (NASDAQ: QUIK), the innovator of ultra-low power programmable sensor processing solutions, announced today that production qualification testing for its new EOS™ S3 sensor processing SoC has been completed successfully. Initial shipments to support pre-production requirements for a tier-one customer are scheduled for later this month.

The EOS S3 sensor processing platform is a multi-core SoC that enables a vast array of concurrent sensor applications, from basic to computationally demanding algorithms for smartphone, wearable, and Internet of Things (IoT) devices. Unlike traditional MCU-based solutions, the EOS S3 sensor processing platform enables sophisticated algorithm partitioning to facilitate the lowest possible power consumption for a designated task.

Advanced sensor algorithms such as voice triggering, motion compensated heart rate monitoring, and indoor navigation can be implemented at significantly lower levels of power consumption than competing MCU-based solutions. Low power consumption enables OEMs to dramatically extend battery life for advanced applications, and with that, significantly enhance the user experience.

"The EOS S3 employs always-on, context-aware sensing capabilities while staying well within the strict power budgets of smartphone, wearable, and IoT designs," said Brian Faith, vice president of worldwide marketing at QuickLogic Corporation. "Now that this leading edge platform has been production qualified, the top-tier OEMs we've been working with know that they can reliably scale up their manufacturing to high-volume production levels."

Key Features

                                                                            
----------------------------------------------------------------------------
              Feature                               Details                 
----------------------------------------------------------------------------
Processor Cores                   - 578 KB of aggregate SRAM for code and   
                                  data storage                              
----------------------------------------------------------------------------
    QuickLogic Proprietary                                                  
    microDSP Flexible Fusion                                                
    Engine                        - 50 KB SRAM for code                     
                                  - 16 KB SRAM for data                     
                                  - Very Long Instruction Word (VLIW)       
                                  microDSP architecture                     
                                  - 30 microWatts/MHz                       
----------------------------------------------------------------------------
    ARM Cortex M4F                - Up to 80 MHz                            
                                  - Up to 512 KB SRAM                       
                                  - 32-Bit, includes Floating Point Unit    
                                  - 75 microWatts/MHz                       
----------------------------------------------------------------------------
    Programmable Logic            - 2,800 Effective logic cells             
----------------------------------------------------------------------------
Integrated Voice                  - Always-On Voice Trigger and Integrated  
                                                                            
                                  Phrase Recognition Capability, based on   
                                  Sensory TrulyHandsFree® technology        
----------------------------------------------------------------------------
                                  - Integrated I2S and PDM microphone input 
                                                                                                
                                                                    with  support  for  mono  and  stereo                    
                                                                    configurations                                                        
----------------------------------------------------------------------------
                                                                    -  Integrated  PDM  to  PCM  conversion                
                                                                    -  Integrated  Sensory  Low  Power  Sound            
                                                                    Detector  (LPSD)                                                      
                                                                    -  Optional  PDM  bypass  mode  to  directly        
                                                                                                                                                        
                                                                    drive  application  processor  or  CODEC            
----------------------------------------------------------------------------
Interface  Support                                                                                                                      
----------------------------------------------------------------------------
        To  Host                                              -  Integrated  SPI  Slave                                        
----------------------------------------------------------------------------
        To  Sensors  and  Peripherals        -  Integrated  SPI  Master  (2X),  I2C,  UART      
----------------------------------------------------------------------------
        To  Microphones                                -  Integrated  PDM  and  I2S                                    
----------------------------------------------------------------------------
----------------------------------------------------------------------------
Additional  Components                                                                                                              
----------------------------------------------------------------------------
        ADC                                                      -  Integrated  12-Bit  Sigma  Delta                      
----------------------------------------------------------------------------
        Regulator                                          -  Integrated  Low  Drop  Out  (LDO),  with  1.8  
                                                                    to  3.6  V  input  support                                        
----------------------------------------------------------------------------
        System  Clock                                    -  Integrated  32  kHz  and  High  Speed                
                                                                    Oscillator                                                                
----------------------------------------------------------------------------
Package  Configurations                                                                                                            
----------------------------------------------------------------------------
        Ball  Grid  Array  (BGA)                  -  3.5  x  3.5  mm  x  0.7  mm,  0.40  mm  ball          
                                                                    pitch,                                                                        
                                                                    -  64-ball,  46  user  I/O's                                    
----------------------------------------------------------------------------
        Wafer  Level  Chip  Scale  Package-  2.7  x  2.4  mm  x  0.6  mm,  0.35  mm  ball          
        (WLCSP)                                              pitch,                                                                        
                                                                    -  42-ball,  27  user  I/O's                                    
----------------------------------------------------------------------------
Development  Environment                      -  Industry  Standard,  IAR  and  Eclipse  IDE    
                                                                    Plugin                                                                        
----------------------------------------------------------------------------
Software  Support                                    -  Supports  Android  Lollipop  and                      
                                                                    Marshmallow  operating  systems                          
----------------------------------------------------------------------------
                                                                                                                                                        
 

1 | 2  Next Page »



Review Article Be the first to review this article
CST: Webinar November 9, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise