Avery Design Systems Announces SimXACT 3.0 for Improved X-Verification

TEWKSBURY, Mass. — (BUSINESS WIRE) — June 6, 2016 — Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of release 3.0 of its patented SimXACT analysis solutions including major new features for analyzing and automatically eliminating X bugs in gate-level design simulation.

SimXACT automates the tedious process of analyzing X propagations in gate-level simulations due to RTL vs gate-level mismatches arising from X-optimism problems and gate-level simulator X-pessimism handling in glue logic and gated clocking and overly pessimistic library cell modelling. SimXACT’s hybrid formal analysis runs with your normal logic simulator and proves and then on-the-fly fixes any false Xs arising from X pessimism during the actual simulation run. SimXACT also provides an X analysis to debug X bugs from RTL vs gate-level simulation mismatches.

A new design and library analysis feature has been added to improve setup process by selecting the best SimXACT runtime options for performance based on design styles and to analyze SUDP models of sequential devices to isolate X-pessimism issues from inadequate models.

A design database has been added to cache initial analysis for use on subsequent runs of the full testsuite regression. Overall performance and memory has each been improved by more than 2X over prior releases. This makes analyzing designs of more than 10M DFFs possible without the need to divide the analysis into steps.

Finally to deal with X propagations arising from X-optimism issues caused by non-reset DFFs corrupting the state of downstream DFFs which previously held deterministic values after reset during functional simulation, SimXACT adds a built-in assertion to monitor DFFs for this potential RTL X bug and generates a time 0 random deposit that more closely tracks actual hardware semantics during the gate-level logic simulation.

Finally an XTrace database has been added along with a TCL-based sequential backtrace commands to “root cause” X propagations back to X sources. Using event-based X propagation analysis X sources can be searched back 100s to 1000s of clock cycles or even back to reset time.

Visit us at the Design Automation Conference (DAC) June 6-9 in booth #800.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI CSI, DSI, Soundwire, and Unipro, DDR/LPDDR, HBM, HMC, ONFI/Toggle, NVM Express, SATA Express, eMMC, SD/SDIO, CAN FD, and I2C standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.



Contact:

Avery Design Systems
Chris Browy, 978-851-3627
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