Hitachi Adopts Cadence AMS Model-Based Methodology and Tools for Mixed-Signal Design Verification

Accelerated mixed-signal verification by 160X for one of its largest designs and reduced full-chip simulation time to 30 minutes

SAN JOSE, Calif., June 2, 2016 — (PRNewswire) — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Hitachi, Ltd. (TSE:6501) has adopted a Cadence® Analog Mixed-Signal (AMS) model-based methodology and tools to shorten the verification cycle for one of its largest mixed-signal design projects. By upgrading its previous transistor-level methodology to a model-based methodology, Hitachi successfully accelerated mixed-signal verification for this project by 160X and reduced full-chip simulation time to 30 minutes. The results were achieved by comparing the transistor-level and the model-based methodology on the same four CPUs. The significant reduction in the verification cycle time provided Hitachi with the ability to meet time-to-market goals for designs that integrate both analog and digital functions.

Cadence Logo

With its previous transistor-level methodology, Hitachi predominantly relied on block-level verification followed by tuning analog-digital interfaces to ensure full-chip functionality, which typically required multiple, costly iterations. By using a Verilog-AMS real number modeling and simulation flow supported by a full set of Cadence tools—Virtuoso® Analog Design Environment (ADE), Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Virtuoso AMS Designer and Incisive® Enterprise Simulator—Hitachi reduced iterations and met its accuracy requirements, ultimately speeding time to market.

For more information on the Cadence tools, please visit www.cadence.com/news/hitachi.

"We've had a trusted partnership with Cadence for many years, and our effective collaboration produced a design environment that significantly improved our productivity and helped us achieve design goals," said Satoshi Ueno, director of Design Engineering Second Department, Technology Development Operation 1, IT Platform Products Management Division, Information and Communication Technology Business Division at Hitachi, Ltd. "Cadence has the behavioral modeling expertise, methodology and tools that we needed to reduce our verification time and enable us to thoroughly verify our design—not just at the block level, but at the full-chip level, which includes sensitive analog-digital interfaces. The gains achieved have had a positive impact on our business, and we also plan to evaluate the Cadence tools and methodology for medical applications and various other system applications."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Incisive, Spectre and Virtuoso are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
408-944-7039
Email Contact

Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO

 

 

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/hitachi-adopts-cadence-ams-model-based-methodology-and-tools-for-mixed-signal-design-verification-300278500.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Hitachi, Ltd.
Web: http://www.cadence.com




Review Article Be the first to review this article
 True Circuits: Ultra PLL

Aldec Simulator Evaluate Now

Featured Video
Jobs
Design Verification Engineer for Cirrus Logic, Inc. at Austin, TX
ASIC Hardware Engineer for BAE Systems Intelligence & Security at Arlington, VA
Senior DSP Firmware Engineer for Cirrus Logic, Inc. at Austin, TX
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
Acoustic Systems Test Engineer for Cirrus Logic, Inc. at Austin, TX
Upcoming Events
Essentials of Electronic Technology: A Crash Course at Columbia MD - Jan 16 - 18, 2018
Essentials of Digital Technology at MD - Feb 13 - 14, 2018
IPC APEX EXPO 2018 at San Diego Convention Center San Diego CA - Feb 24 - 1, 2018
CST: Webinar series
TrueCircuits: UltraPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise