Pulsic at DAC 2016: Overcoming the Traditional Bottlenecks in Transistor-Level and Cell-Level Custom Design Flows

Pulsic Animate offers unique automated analog layout for area estimation, layout simulation and layout

SAN JOSE, Calif. — (BUSINESS WIRE) — May 24, 2016 — Typically, there are three phases in custom design flows where time to final layout has been a bottleneck: area estimation, layout / simulation cycle and final layout. Pulsic, the premier provider of physical design tools for precision design automation, will demonstrate solutions to overcome those bottlenecks at DAC 2016: Pulsic Animate™ and Pulsic Unity™ Chip Planner.

Pulsic Animate surpasses traditional approaches to automating transistor-level IC design, which have attempted to improve on portions of the design flow, but have not managed to generate near “manual-quality” layout without significant user intervention. Animate is the first complete automated layout system built from the ground up for transistor-level analog and custom-digital design. Animate overcomes layout bottlenecks by delivering an easy-to-use flow that reads in a schematic, automatically extracts design constraints, and employs patent-pending, multi-threaded PolyMorphic™ technologies to very quickly produce abstracted “Blueprint” representations of the designs. Many different “Blueprints” are generated in minutes or seconds. These layout “Blueprints” are guaranteed to contain no opens or shorts and can therefore be extracted to produce accurate parasitics that can be fed back into simulation. Animate’s constraint recognition capability automatically generates constraints based on netlist topology analysis, eliminating the need for manual constraint entry and management.

Layout “Blueprints” can be saved to an OpenAccess database and modified by the user to produce high-quality, fully placed and routed, detailed layouts in a fraction of the time taken using a traditional approach.

For more detailed information on Pulsic’s automated analog layout solution, see http://www.pulsic.com/Animate/. For an exclusion demonstration of Pulsic’s Animate while at DAC, click here.

“For too long now, manual layout has persisted in analog design because previous efforts at automation could not approach the level of quality offered by manual designers,” said Mark Williams, co-founder and CEO, Pulsic. “Animate provides value in multiple areas across the design flow. Since the introduction of Animate last year, we have been receiving accolades from both circuit designers and layout engineers who are able to do accurate simulations early in the design process and to get to faster layout closure with high quality of results.”

Pulsic Unity Chip Planner is the first and only hierarchical, top-down and bottom-up floorplanner built for cell-level custom design. Although automated floorplanners are a part of standard digital design flows, they do not address all the needs of custom designers. Custom designers face unique challenges, such as large hard-IP blocks, analog content, and few metal layers available for routing. At leading-edge nodes (28 nm and below), process rules constrain designs in new ways, and the extreme aspect ratios of the routed wires and highly resistive metals make understanding parasitics critical.

Unity Chip Planner enables custom design teams to manage growing complexity while accelerating design closure and improving design quality. By providing a high level of automation, Unity Chip Planner gives accurate results quickly and enables custom design teams to respond to netlist changes quickly and easily. In addition, Unity Chip Planner can produce early estimated parasitic extraction data from an unrouted -- or partially routed -- floorplan, allowing multiple architectures to be explored and validated without time-consuming detailed implementation of the layout.

Unity Chip Planner provides all the necessary tools and technologies within a fully integrated floorplanning environment. The guided flow offered in Unity Chip Planner helps ensure faster design closure with successful results every time. For more detailed information, please visit: http://www.pulsic.com/products/pulsic-planning-solution/unity-chip-planner/. For an exclusion demonstration of Pulsic’s Unity Chip Planner while at DAC, click here.

The 53rd DAC will be held in the Austin Convention Center in Austin, Texas from Sunday, June 5 to Thursday, June 9. DAC is the premier conference devoted to the design and automation of electronic systems, offering attendees outstanding training, education, exhibits and networking opportunities. Visit Pulsic in Booth #1439.

About Pulsic

Pulsic is an electronic design automation (EDA) company offering production-proven chip planning and implementation solutions for extreme design challenges at advanced nodes. Leading semiconductor companies use Pulsic’s physical design software to achieve significant improvements in their design productivity through layout automation using Pulsic’s advanced solutions. Complementary to existing design flows, standards, and databases, Pulsic technology delivers handcrafted quality faster than manual design or other EDA software solutions. Pulsic has delivered successful tapeouts for IDMs and fabless customers in the memory, FPGA, custom digital, LCD, imaging, and AMS markets worldwide. For more information, please visit http://www.pulsic.com. Follow us on twitter  @Pulsic.

Pulsic Unity, Pulsic Unity Chip Planner and Pulsic Animate are trademarks of Pulsic Limited. Any other trademarks or trade names mentioned are the property of their respective owners.

1 | 2  Next Page »

Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
More Editorial  
Test Development Engineer(Job Number: 17001697) for Global Foundaries at Santa Clara, CA
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Verification Engineer for Ambarella at Santa Clara, CA
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy