Reinforces Verific’s Innovative Business Model to Jumpstart Design Automation Entrepreneurial Efforts
ALAMEDA, CALIF. – May 24, 2016 – Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF parsers, will showcase startup ventures Austemper Design, Innergy Systems and Tortuga Logic in its booth (#538) during the Design Automation Conference (DAC) June 5-9 in Austin, Texas.
Each will demonstrate versions of its design automation software Tuesday, June 7, and Wednesday, June 8, at:
10 a.m.-noon –– Austemper will showcase the way it adds robustness to intellectual property (IP) blocks by automatically inserting safety features required to meet medical, automotive and industrial industry regulations
noon-2 p.m. –– Innergy Systems will demonstrate power estimation software
2-4 p.m. –– Tortuga Logic, a hardware security thought leader, will highlight Sentintel™, the first industry security language, and Prospect™ Security Property Verification Environment for thorough Hardware Security Assessments.
“Many EDA startups require SystemVerilog or VHDL input for their toolset and that brings them to us,” says Rob Dekker, Verific’s chief technology officer. He adds that Verific enables them to focus on their expertise by providing technology that’s already well used in production environments. “We welcome the opportunity to work with startups and give them access to our parsers. That way, we keep a keen eye on new design automation activities. And, when a startup knocks on the door of Intel, NVIDIA and other industry giants and its SystemVerilog support is from Verific, they automatically mark that checkbox as done.”
“Venture capital and angel funding are not as readily available as they once were, though that doesn’t mean there aren’t any good ideas,” remarks Rick Carlson, Verific’s vice president of sales. “We view our relationships with startups as a positive way to encourage and foster entrepreneurism in our industry. Some may follow in the footsteps of Archpro, Calypto, Carbon, Certess, Denali, EVE, Forte, Jasper, NextOp, Oasys, Rocketick, Sequence, Veridae, Yogitech, and Zerosoft, all of whom worked with Verific and had successful exits.”
Verific invites attendees to view demonstrations of its parsers in DAC Booth #538 and to pick up this year’s giraffe giveaway. DAC will be held June 5-9 between10 a.m. and 6 p.m. at the Austin Convention Center. Contact Carlson to schedule a demonstration. He can be reached at (970) 948-9650 or via email at Email Contact or visit Verific’s website located at: http://www.verific.com
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: Email Contact Website: www.verific.com
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