RFEL launches new Fractional Rate Resampler IP core at EW Europe

Newport, Isle of Wight, UK, Apr 27, 2016 – RFEL will be launching its latest core at EW Europe. www.eweurope.com   The new Fractional Rate Resampler IP core, which was originally part of the company’s multi-award winning ChannelCore Flex™ product, is now offered as a stand-alone IP core for FPGAs in response to customer requests.

The core enables input data rates to be modified to manage systems with multiple clock domains, unifying all signal paths onto a single clock domain.  Arbitrary input data rates can be easily matched to support the data rates required for following algorithms such as DEMODS or CODECs.  Equally, the core can be used in post filtering applications so that data rates can be optimally set to match the data rate to the output bandwidth.

This makes the core ideal for Digital Signal Process systems development, harmonising over multiple clock domains, clock domain crossing, and algorithm integration that are particularly useful for COMINT, SIGINT, Electronic Warfare (EW), radar, sonar and similar security and surveillance applications.

The architecture uses an Interpolator followed by a Low Pass Filter and a final Decimator stage, leading to the output.  This enables the core to change the sample rate of a signal by an integer ratio of L/M, where L is the up-sampling interpolator factor and M is the down-sampler decimator factor.  The core can be built as a static configuration (with fixed L and M values) or as run-time programmable variant (where the values for L and M can be modified in real-time).  The architecture has an arbitrary internal parallelism and so can support data rates that are limited only by the resources of the FPGA that it is running on.  Other key features are a complex wideband input, a high-performance filtering stage and variable bit widths. 

RFEL’s Fractional Rate Resampler is available as an evaluation core that allows users to integrate the solution into their wider designs for assessment.  The evaluation core operates for 30 minutes, before requiring FPGA reconfiguration and can be simply upgraded to the full version by the purchase of a licence key.  It is available to target Xilinx and Altera FPGAs. 

Dr Alex Kuhrt, RFEL’s CEO, said, “RFEL is leader in the field of providing specialist IP for EW.  We are constantly reviewing and improving our portfolio of IP designed for EW applications.  This Fractional Rate Resampler is a powerful tool in the EW System Designer’s toolkit.”



Read the complete story ...


Review Article Be the first to review this article

EMA:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Retail Therapy: Jump starting Black Friday
Peggy AycinenaIP Showcase
by Peggy Aycinena
REUSE 2016: Addressing the Four Freedoms
More Editorial  
Jobs
ACCOUNT MANAGER MUNICH GERMANY EU for EDA Careers at MUNICH, Germany
Principal Circuit Design Engineer for Rambus at Sunnyvale, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Upcoming Events
Zuken Innovation World 2017, April 24 - 26, 2017, Hilton Head Marriott Resort & Spa in Hilton Head Island, SC at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy