Kandou Licenses Glasswing SerDes Technology to Marvell

LAUSANNE, SWITZERLAND - Kandou Bus announced today that their Glasswing™ chip-to-chip link technology has been licensed by Marvell Technology Group for use in a variety of future multi-chip products. Based on Kandou’s CNRZ-5 Chord™ signaling architecture, Glasswing delivers high bandwidth signaling at very low power and is ideally suited for short links inside and outside a package. Glasswing is the world’s first SerDes proven in silicon that is capable of delivering 1Tbps bandwidth at <1 watt, paving the way for fundamental architectural shifts in power savings in devices ranging from cell phones to enterprise and high-performance computing platforms.

“Marvell provides a wide variety of world-class consumer and enterprise silicon solutions and we are excited to collaborate with them to realize the capabilities of our Chord signaling technology,” said Amin Shokrollahi, Founder and CEO of Kandou. “Marvell’s leadership in low-power, complex system-on-chip design architecture and its system-level expertise are well known. Marvell and Kandou share a vision to provide system architects unprecedented flexibility to optimize for performance, power, signal integrity and cost.”

“We are very proud of this collaboration and believe that our work with Kandou further reflects our leadership in chip design,” said Dr. Zining Wu, Chief Technology Officer at Marvell Semiconductor, Inc. “Glasswing provides a high-speed interconnect with ultra-low power consumption that is ideal for our products. Glasswing’s technology is designed to enable the combination of multiple chips in a single package or multiple packages and provide an optimal mix of die in different process nodes, helping to usher in the new era of silicon photonics.”

The version of Chord signaling employed in Glasswing, called CNRZ-5 coding, delivers 5 bits over 6 correlated wires for a total bandwidth of 125Gbps per channel. Total link power consumption of Glasswing built in TSMC’s 16nmFF foundry process is about 700 femtojoules/bit. The link achieves a BER of < 10-15 or better at the targeted data rate of 25GBaud.




Review Article Be the first to review this article
Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Job Openings: Can EDA Predict the Future
More Editorial  
Jobs
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
Verification Engineer for Ambarella at Santa Clara, CA
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
ASIC Design Engineer for Ambarella at Santa Clara, CA
Engr, Elec Des 2 for KLA-Tencor at Milpitas, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy