SUNNYVALE, CALIF. – Mar. 29, 2016 –
Real Intent, whose advanced verification solutions accelerate electronic design sign-off, eliminate complex failures in SoCs, and lead the market in performance, capacity, accuracy and completeness
Will showcase its Ascent™ and Meridian™ products for accelerating advanced sign-off in the Designer Expo at the Cadence User Conference 2016 (CDNLive Silicon Valley) on Tuesday next week. Ascent tools provide the fastest early functional verification for clean RTL prior to simulation and synthesis; they find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, improving QoR and productivity for design teams. Real Intent’s comprehensive low-noise reporting makes debug fast and efficient for linting, and X-verification and optimization. Meridian products accelerate sign-off verification of clock domain crossings and SDC in billion-gate SoC designs, delivering unmatched speed, capacity, precision and low-noise reporting.
CDNLive Silicon Valley brings together a record number of Cadence® technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for designing advanced silicon, SoCs, and systems.
Tuesday, Apr. 5, 2016 (12:30pm – 2pm and 5:30pm – 7pm)
Designer Expo, Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, Calif. 95054
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and sign-off of electronic designs. Real Intent’s comprehensive CDC verification and advanced RTL analysis eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
Real Intent and the Real Intent logo are registered trademarks, and Ascent, Meridian and iDebug are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
CDC Clock Domain Crossing
QoR Quality of Results
RTL Register Transfer Level
SDC Synopsys Design Constraints
VHDL VHSIC High-level Design Language
Sarah Miller for Real Intent
ThinkBold Corporate Communications