EnSilica launches Kalman Filter acceleration IP core for advanced driver assistance systems (ADAS)

Wokingham, UK – March 22, 2016.  EnSilica, a leading independent provider of semiconductor solutions and IP, has launched a Kalman Filter acceleration IP core for use in situational awareness radar sensors for advanced driver assistance systems (ADAS), such as electronic stability control systems, pre-crash impact mitigation, blind spot detection, lane departure detection, and self-parking. The Kalman Filter acceleration IP core, which is part of EnSilica's emerging automotive IP portfolio that also includes pipelined FFT and Constant False Alarm Rate (CFAR) cores, provides an estimated speed improvement over software-only solutions of up to 10x.

Kalman filtering is used in sensor-based ADAS as part of the radar tracker in order to smooth out position and velocity measurements obtained from the radar sensors and front-end DSP unit. The development of EnSilica’s Kalman Filter acceleration IP core follows the guidelines necessary for integration with devices adhering to the ISO 26262 functional safety standard for road vehicles. It supports both classical Kalman filtering (KF) and extended Kalman filtering (EKF), the latter being applicable when there is a non-linear relationship between the target’s Kalman state and the radar measurements.

The compact, low gate-count architecture of EnSilica’s Kalman Filter acceleration IP core enables the computationally intensive matrix operations involved in Kalman filtering to be cost-effectively offloaded from the CPU. It operates on Range (distance), Doppler (velocity) and Azimuth (positional) measurements and applies Kalman filtering in order to predict the target’s position in the next time interval. It combines the radar measurements with a dynamic motion model for enhancing the target position and velocity estimates with forward prediction, allowing false alarm measurements to be discarded. The Kalman Filter acceleration IP core also provides a generic algorithm framework for fusing measurements from different sensors into a single target track.  

For a typical automotive radar system, EnSilica’s Kalman Filter acceleration IP core can provide a state update computation in about 10µs. This enables a large number of target tracks to be maintained at any given time, as this level of processing latency is very short compared to a usual radar measurement cycle, which is in the order of a few milliseconds. The core undertakes five main computational steps - setting the initial values, prediction of the state and error co-variance, computation of the Kalman gain, computation of the estimate and computation of the error co-variance - using floating point arithmetic in order to maintain numerical stability and provide identical results to a software implementation. RAM blocks of typically 8Kbits, depending on the matrix dimensions, are used to hold the computational matrices.

“Kalman Filter tracking is essential to radar-based advanced driver assistance systems as well as drones, UAV and UGV requiring fast and responsive situational awareness using multiple sensors,” said Ian Lankshear, CEO of EnSilica. “Integrating the EnSilica Kalman Filter acceleration IP core in the front-end DSP unit for the computationally demanding processing tasks of Kalman filtering provides a cost-effective ASIC or FPGA solution for enhancing overall system performance and releasing valuable CPU resources.”

About EnSilica

EnSilica was founded in 2001 and has a strong track record of success in delivering ASIC and FPGA based solutions to semiconductor companies and OEMs worldwide. The company is headquartered in the UK and has subsidiaries in India and the USA. The company is a specialist in low-power ASIC design and complex FPGA-based embedded systems. In addition to supplying IP and turnkey ASIC/FPGA development and supply, EnSilica also provides point services to companies with in-house ASIC design teams. These services include system engineering, analog and mixed signal design, and advanced verification using UVM, DFT and physical implementation.  For further information about EnSilica, visit http://www.ensilica.com.


Read the complete story ...

Review Article Be the first to review this article
CST Webinar Series


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Acquiring Mentor: Four Good Ideas, One Great
More Editorial  
SENIOR ASIC Design Engineer for TiBit Communications at Petaluma, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Sr. staff ASIC Design Engineer -2433 for Microchip at San Jose, CA
Upcoming Events
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
2016 International Conference On Computer Aided Design at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
ICCAD 2016, Nov 7-10, 2016 at Doubletree Hotel in Austin, TX at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
Electric&Hybrid Aerospace Technology Symposium 2016 at Conference Centre East. Koelnmesse (East Entrance) Messeplatz 1 Cologne Germany - Nov 9 - 10, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy