Analog Bits to Demonstrate Half-Power SERDES(TM) at TSMC's San Jose Technology Symposium


SAN JOSE, CA, (Marketwired) - March 15, 2016 - Analog Bits ( will be demonstrating their latest half power SERDES IP at booth #412 at TSMC's Technology Symposium in San Jose, CA. SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high speed interface for a broad range of applications from storage to display. Lately, increased requirements for higher speed SERDES has battled against increased power requirements. Analog Bits has revolutionized SERDES IP by cutting the power in half while concurrently supporting multiple standards such as PCIe Gen 3, Gen 4, USB3.1, HMC, SAS and more -- all while allowing the highest flexibility for on-die placement.

WHAT: Analog Bits' 16nm Half-Power SERDES™ IP solutions

-- Passing JTOL tests using Keysight's latest J-BERT at 16Gbps with less than 750fs RMS jitter
-- Multiprotocol including PCIe Gen 3/4, HMC 2.0, 10G-KR, USB 3.1
-- Small die size impact
-- Location on any die side

WHEN: TSMC Technology Symposium 2016 Expo: March 15, 2016


About Analog Bits: Founded in 1995, Analog Bits, Inc. (, is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs. Products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O's as well as specialized memories such as high-speed SRAMs and TCAMs. With billions of IP cores fabricated in customer silicon, from 0.35-micron to 16/14-nm processes, Analog Bits has an outstanding heritage of "first-time-working" with foundries and IDMs.

C ontacts:
Will Wong
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