Trilinear Technologies Delivers Next Generation DisplayPort Link Controllers

Includes full support for DisplayPort 1.3a and Embedded DisplayPort 1.4

PORTLAND, Ore. – Trilinear TechnologiesTM, Inc., a leading provider of imaging and display intellectual property (IP) cores continues to advance the state of the art in DisplayPortTM link controller cores. Building on the highly successful line of DisplayPort link controller cores originally introduced in 2007, the Trilinear VF-111T DisplayPort Transmitter and VF-117R DisplayPort Receiver cores have been updated to include full support for the Video Electronic Standards Association (VESA) DisplayPort 1.3a standard and the Embedded DisplayPort 1.4 standard.  With the latest round of improvements, Trilinear has added compliance with the latest VESA standards and support for multiple silicon PHY implementations available in process nodes from 55nm to 14nm.  Both cores are currently implemented for evaluation in Xilinx FPGAs.

The new generation of Trilinear DisplayPort link controllers provides a highly advanced set of functionality including complete support for DisplayPort 1.3a featuring the HBR3 data rate, Multiple Stream Transport (MST) and HDCP 2.2 encryption and decryption engines.  Improved support for Embedded DisplayPort 1.4 has also been included with Panel Self-Refresh modes 1 and 2, Advanced Link Power Management, Multi-Touch over AUX as well as full support for all secondary channel packet types. As with the previous generation of DisplayPort solutions, the new link controllers are highly configurable and include full standards compliance.  Both cores are available for licensing now. The IP is silicon proven licensed by multiple lead customers.

As with all previous generations of the Trilinear DisplayPort link controllers, the latest cores provide a unique internal architecture that allows integration into both FPGA and ASIC target environments with no loss of performance.  This allows for reliable ASIC prototyping as well as the deployment of production quality solutions in FPGA.  Low CPU overhead for each core and standard interfaces such as the AMBA APB-3 allow for easy integration into existing or new designs.

In addition to the advanced functionality of the new DisplayPort Intellectual Property cores, Trilinear Technologies has included support for a wide range of silicon PHY solutions from multiple partners.  “Selecting the proper PHY for integration with a DisplayPort link controller is a major consideration in any DisplayPort design”, said Carl Ruggiero, CEO for Trilinear Technologies.  “Our engineers have made great strides in providing support for a wide range of solutions from 55 nanometer down to 14 nanometer process targets.  The fact that we support multiple third party PHY implementation as well as customer developed implementations make these cores some of the most versatile in the market.”

The Trilinear DisplayPort cores are available for demonstration on the FPGA-based Cobra Development System with a complete Software Development Kit (SDK) featuring the DisplayPort-compliant Link Manager. The Cobra development system supports full transmitter and receiver core validation environments and allows for real time testing of all supported lane count and link rate configurations.

Availability and Pricing 

The Trilinear DisplayPort VF-111T and VF-117R link controllers have been in production since 2007.  The latest generation cores supporting DisplayPort 1.3a are now available for customer shipment. They are shipped with a Cobra Development Board and a complete SDK featuring the DisplayPort-compliant Link Manager. For more information about the product, its pricing, and how to purchase, go to http://www.trilineartech.com.

About Trilinear Technolgies, Inc. 

Trilinear Technologies Inc., headquartered in Portland, Ore. and privately funded, is a premier provider of high definition (HD) video hardware IP cores for ASIC implementation and FPGA prototyping. The company services the broadcast, consumer display, medical, mobile devices, military, and security markets. Trilinear’s IP cores enable customers producing high quality chips to enjoy faster product design, shorter time-to-market, and overall cost reduction. The company sells its products through a network of distributors. For more information about the company and its products, please visit http://www.trilineartech.com.




Review Article Be the first to review this article
CST: Webinar September 14, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Real Intent: Leveraging on Investments
More Editorial  
Jobs
Field Application Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise