Arasan Announces USB 2.0 PHY in Ultra Low Power TSMC 40LP

San Jose, CA. -  Arasan’s USB 2.0 PHY has been designed to target mobile devices and the automotive market. This IP expands Arasan’s library of nodes, now available from 180nm to 28nm from major foundries including automotive grade qualifications. Ubiquitous in PCs, USB 2.0 is now the charging and media transport interface for billions of mobile products from Smartphones to headphones. USB is pervasive in all electronic segments including automotive, enterprise, medical and industrial applications.

Arasan entered the USB 2.0 PHY IP market with the acquisition of the silicon-proven Mentor technology. Arasan engineering successfully integrated the technology into Arasan’s design flow to ensure interoperability with its controllers. Arasan is the only company to offer the complete suite of USB 2.0 IP products including the USB 2.0 Host, Hub, Device, OTG, and PHY. Arasan also offers the HSIC option for chip to chip connections over USB.

“With 20 years of USB experience and over 100 USB Semiconductor Licensees, Arasan is the Total USB IP Solution provider”, Chari Santhanam, Arasan VP. of Engineering and a recognized expert on USB IP.

Availability

Arasan’s USB 2.0 IP PHY and USB 2.0 controller IP are available for immediate delivery. Contact sales@arasan.com for more information.

About Arasan

Arasan Chip Systems is a leading provider of Total IP Solutions for mobile and the next generation of Smart applications from home to automobile. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for Ethernet, MIPI, PCIe, USB, UFS, SD, SDIO, eMMC, and UFS. Arasan’s Total IP products serve system architects and chip design teams in applications that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.




Review Article Be the first to review this article
CST: Webinar October 19, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Field Application Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
Preparing for the Cognitive Era: Education, Occupation and You at SJSU Student Union Theater 211 South 9th Street San Jose CA - Oct 18, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise