Media Alert: Cadence to Showcase Design Solutions at TSMC's 2016 Technology Symposium

SAN JOSE, Calif., March 8, 2016 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it is scheduled to showcase 10nm FinFET (10FF) and 16nm FinFET Plus (16FF+) advanced-node technologies that optimize customer designs and manufacturing efficiency at this year's TSMC Technology Symposium in booth 103 on March 15, 2016, in San Jose, Calif.

Cadence Logo. (PRNewsFoto/Cadence Design Systems, Inc.) (PRNewsFoto/CADENCE DESIGN SYSTEMS_ INC_)

What:
Cadence is planning to hold several demonstrations across a broad range of technology solutions including:

  • Library characterization combining the foundry-trusted Virtuoso® Liberate™ Characterization Solution and the silicon-proven Spectre® Circuit Simulation Platform
  • Circuit simulation with Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS) and Virtuoso AMS Designer for analog, RF design, FastSPICE and mixed-signal system-on-chip (SoC) verification
  • Wafer-level chip-scale packaging (WLCSP) flow from design to verification signoff using Cadence® SiP Layout and Cadence Physical Verification System (PVS)
  • Cadence and TSMC's innovative solutions for custom design flows at 10nm with Virtuoso Advanced Node
  • Cadence full-flow digital solution for best-in-class power, performance, and area (PPA) and a fast path to design closure
  • Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, and Quantus™ QRC Extraction Solution for 10nm silicon-proven signoff with tightly-integrated Innovus™ Implementation System and Virtuoso Variation-Aware Implementation Option flows for 10X faster design closure
  • Layout dependent effect (LDE) and PVS acceleration for 10nm analog and digital designs using Virtuoso and Innovus solutions
  • Latest multi-link and multi-protocol PHY for PCI Express® (PCIe®) 4.0, mixing networking protocols with a single macro, offering long-reach and high-power efficiency
  • Eye diagrams for test chips operating at 3200Mbps on 16FF+ and 2400Mbps on 28HPC process nodes
  • Complete Internet of Things (IoT) subsystem with Cadence SoundWire for MIPI®, QSPI, I2C, and SPI for rapid system development and reduced integration effort

When:
March 15, 2016

Where:
Booth 103
TSMC 2016 Technology Symposium
San Jose McEnery Convention Center
150 West San Carlos Street
San Jose, CA 95113

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at http://www.cadence.com.

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Spectre and Virtuoso are registered trademarks, and Innovus, Liberate, Quantus, Tempus and Voltus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. PCI Express and PCIe are registered trademarks of PCI-SIG. MIPI is a registered trademark owned by MIPI Alliance. All other trademarks are the property of their respective owners.

Cadence Newsroom
408-944-7039
Email Contact

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To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/media-alert-cadence-to-showcase-design-solutions-at-tsmcs-2016-technology-symposium-300231218.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com


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