Diversified portfolio of verification intellectual properties (VIPs) supported in all simulation and acceleration platforms
SAN DIEGO, CA – February 26, 2016 – Simulation is becoming a major bottleneck in the development of large, complex system-on-chip (SoC) designs. Verification is taking longer and simulations are running slower as design complexity is increasing. Simulation acceleration combines functional simulation with emulation hardware and delivers the performance needed for validating today’s complex designs, including billion-gate SoCs. But without easy porting from a simulation flow to an acceleration flow, productivity gains are swallowed up by additional engineering resource utilization and an increase in overall SoC validation time, badly impacting time to market.
SmartDV, the verification intellectual property (VIP) company, is helping customers realize simulation acceleration productivity gains by releasing VIPs that support all acceleration platforms – Mentor Veloce, Cadence® Palladium®, Synopsys Zebu® and customers’ in-house custom platforms. SmartDV simulation VIP users can reuse sequence libraries and test cases from simulation flows. APIs are compatible with simulation VIP, increasing the efficiency of engineers.
AT DVCon, SmartDV’s management and technical team is available to discuss and demonstrate support for 20+ SimXL VIPs: AMBA APB, AMBA AHB , AMBA AXI, LPDDR3 , LPDDR4, DDR3, DDR4, MIPI CSI2, Ethernet, Interlaken, UART, I2C, SPI, MIPI UFS , MIPI UNIPRO, MIPI MPHY , MIPI CPHY, USB , HMC, HBM, MIPI DSI, SDIO, eMMC, DPORT and HDMI. These VIPs deliver the same functionality and timing that customers now experience with SmartDV’s simulation VIPs. Architecture of all SmartDV VIPS will remain the same across the simulation and acceleration flow. An additional 12 SimXL-ready VIPs will be released at the end of March. For more information on SmartDV’s VIP portfolio, see http://www.smart-dv.com/products.html
“More and more of our customers are meeting short time-to-market windows by opting for acceleration to improve performance,” said Deepak Kumar Tala, CEO and managing director of SmartDV. “By providing them with a diverse portfolio of commonly-used SmartDV VIPs that now support simulation acceleration on any platform, we hope to help design teams deliver on the productivity promise that simulation acceleration offers.”
SmartDV is in Booth #404 at the 2016 Design and Verification Conference ( DVCon), which takes place from February 29 until March 3 at the DoubleTree Hotel in San Jose, CA.
SmartDV Technologies creates high quality standard and custom protocol verification intellectual property (IP) products designed to work with coverage-driven verification and simulation acceleration flows. The company’s mission is to provide high quality IP along with industry-best support at lower cost and to help remove limited licensing constraints, speeding up regressions and time to market. Each verification IP (VIP) is shipped with a compliance test suite and complete functional coverage model, further accelerating time to market. Each VIP also is independently developed and verified against external design IP for highest quality. SmartDV VIPs are platform independent, supporting all major simulators and acceleration platforms.
SmartDV VIPs are 2-4x faster to compile and simulate than competitive VIPs. SmartDV has customers from wireless/mobile, storage, automotive, memory, networking and other domains.
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Linda Marchant, Cayenne Communication, 919-451-0776, Email Contact