SUNNYVALE, CA--(Marketwired - January 29, 2016) -
Will explore industrial-strength sign-off for SOC-sized FPGAs during a free hour-long webinar on Feb. 3, 2016 -- Ensuring Robust RTL Sign-off for Altera FPGAs. Verification at the RTL stage of development is essential for saving valuable debug time after implementation. The integration of complex digital logic with third-party IP makes verification of clock-domain crossing and reset-domain crossings mandatory for sign-off, because CDC errors are especially difficult to debug. This webinar, accessible to registered viewers worldwide, covers syntax and semantic checks, automatic formal analysis and clock-domain crossing verification. It explores a solution from Real Intent that reflects practical experience by FPGA designers.
The webinar will include design examples using Stratix® 10 FPGAs and SoCs to show RTL sign-off requirements. Built on Intel's 14nm TriGate process and featuring the HyperFlex core fabric architecture, Stratix 10 FPGAs and SoCs deliver breakthrough advantages in performance, power efficiency, density, and system integration. Altera is now a part of Intel Corporation.
Wednesday, Feb. 3, 2016, 10-11 a.m. Pacific Time U.S. The webinar also will be archived for convenient future viewing. Please register here.
About Real Intent
Companies worldwide rely on Real Intent's EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent's comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit http://www.realintent.com for more information.
Stratix is a registered trademark of Altera Corporation, now part of Intel Corporation. Real Intent and the Real Intent logo are registered trademarks, and Meridian, Autoformal and Ascent are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
CDC Clock Domain Crossing
EDA Electronic Design Automation
FPGA Field-Programmable Gate Array
QoR Quality of Results
RTL Register Transfer Level
SoCs Systems on Chip
Press contact: Sarah Miller for Real Intent ThinkBold Corporate Communications 231-264-8636 Email Contact