HiSilicon Adopts Cadence Innovus Implementation System for Production DSP Designs

Innovus Implementation System enabled HiSilicon to achieve 1.2GHz performance while reducing area by 20 percent

SAN JOSE, Calif., Jan. 18, 2016 — (PRNewswire) — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that HiSilicon has completed a successful evaluation of the Cadence® Innovus™ Implementation System that led to the adoption of the solution for 28nm and advanced node FinFET digital signal processor (DSP) design projects. The Innovus Implementation System enabled HiSilicon to achieve an optimal target performance of 1.2GHz while creating a 20 percent smaller design when compared with its previous solution.

Cadence Logo.

The Innovus Implementation System handles challenging, highly complex designs utilizing technologies such as the GigaPlace™ solver-based placement technology, GigaOpt™ low-power optimization and CCOpt™ concurrent clock and datapath optimization engines. The Innovus Implementation System is built on a massively parallel architecture, allowing core algorithms to utilize multi-threading and distributed computing to provide a significant capacity improvement and speedup on industry-standard hardware. These capabilities enabled HiSilicon to implement multi-million cell blocks without having to rely on design partitioning or hierarchy.

 "We chose to adopt the Innovus Implementation System because it was able to meet our target frequency using significantly less area based on our DSP block design," said Catherine Xia, Dept. Director of COT Design Dept. at HiSilicon. "The Cadence solution is intended for the complex, advanced-node designs that our customers demand, and we can now deliver these designs to the market much faster."

"The Innovus Implementation System was designed to address the capacity and PPA challenges of large complex designs, and we've seen HiSilicon improve both PPA and turnaround time simultaneously," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. "In particular, achieving significant area savings while meeting the maximum desired frequency shortened HiSilicon's implementation schedule and saved related development costs for their large designs."

The Innovus Implementation System is a next-generation physical implementation solution that enables developers to deliver high-quality designs with best-in-class PPA while accelerating time to market. For more information on the Innovus Implementation System, please visit http://www.cadence.com/news/HiSilicon/.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and CCOpt, GigaOpt, GigaPlace and Innovus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
Email Contact

Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO


To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/hisilicon-adopts-cadence-innovus-implementation-system-for-production-dsp-designs-300205388.html

SOURCE Cadence Design Systems, Inc.

Cadence Design Systems, Inc.
Web: http://www.cadence.com

Review Article Be the first to review this article

Featured Video
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Design Verification Engineer for intersil at Morrisville, North Carolina
Applications Engineer for intersil at Palm Bay, Florida
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018
DownStream: Solutions for Post Processing PCB Designs

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise